TPS7A84 - 3A Low-Noise High-Accuracy LDO | Texas Instruments
MPN： TPS7A84 ✓ 啟用中TPS7A84 概覽
An LDO (low-dropout) linear regulator is a voltage regulator that maintains a stable output even when input voltage is very close to the output. As a subclass of linear regulators, LDOs use a pass transistor in its linear region and are essential power management ICs, providing clean, low-noise rails for sensitive analog and digital loads. Hierarchy: LDO -> linear regulator -> voltage regulator -> power management IC.
Key features include 3 A output current, 180 mV maximum dropout, 4.4 uVRMS output noise (0.8 V output) and 7.7 uVRMS at 5.0 V output, and 1% maximum output accuracy over line, load, and temperature. High PSRR rejects upstream switching-converter ripple, and pin-programmable output voltages eliminate external feedback resistors. The BIAS pin enables operation from inputs as low as 1.1 V.
Internally, a precision bandgap reference and low-noise architecture deliver the accuracy and noise performance. Current limit and thermal shutdown protect against faults, while the exposed thermal pad of the 20-pin VQFN (RGR) package supports full 3 A delivery with proper PCB layout. Junction temperature range is -40C to +125C.
Typical applications include powering FPGAs, DSPs, ASICs, SerDes, PLLs, VCOs, and high-speed ADCs/DACs in communications, video processing, medical imaging, and test equipment. Low noise limits power-supply-generated phase noise and clock jitter.
Design tip: ensure adequate input-output headroom, use low-ESR ceramic capacitors, connect BIAS to a higher rail to reduce dropout, and manage thermals at high current and large dropout voltages.
直接替換替代品，適用於 TPS7A84 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
TPS7A84A
✅ 直接替換📋 參考替代品（不在目錄中）
TPS7A8300QRGRRQ1
✅ 直接替換聯絡詢價
查看資料表 →TPS74401
✅ 直接替換📋 參考替代品（不在目錄中）
TPS7A88
⚡ 相同封裝📋 參考替代品（不在目錄中）
TPS7A53B
⚡ 相同封裝📋 參考替代品（不在目錄中）
LT3045
⚡ 相同封裝 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
TPS7A84 最大額定值與電氣特性
| Output Current | 3 A |
| Output Voltage Range (Pin-Programmable) | 0.8 V to 3.95 V |
| Output Voltage Range (Adjustable) | 0.8 V to 5.0 V |
| Input Voltage (no BIAS) | 1.4 V to 6.5 V |
| Input Voltage (with BIAS) | 1.1 V to 6.5 V |
| 壓降電壓 | 180 mV (max) |
| 輸出雜訊 | 4.4 uVRMS (0.8 V out); 7.7 uVRMS (5.0 V out) |
| Output Accuracy | 1% (max) over line, load, temperature |
| PSRR | High PSRR (see datasheet curves) |
| 電源良好輸出 | Yes |
| 工作溫度 | -40C to +125C (TJ) |
| 封裝 | VQFN-20 (RGR) with exposed thermal pad |
| 安裝類型 | Surface Mount |
| Protection Features | Current limit, thermal shutdown |
| 輸出配置 | Positive, adjustable or pin-programmable |
TPS7A84 腳位配置
| 腳位 1 | IN — Input supply voltage |
| 腳位 2 | IN — Input supply voltage |
| 腳位 3 | BIAS — Bias rail for internal circuitry; enables low-VIN operation (1.1 V min with BIAS) |
| 腳位 4 | EN — Enable control input |
| 腳位 5 | PG — Power-good open-drain output |
| 腳位 6 | FB — Feedback input for adjustable output (0.8 V to 5.0 V) |
| 腳位 7 | VSET — Pin-programmable output voltage select |
| 腳位 8 | GND — Ground |
| 腳位 9 | OUT — Regulated output voltage |
| 腳位 10 | OUT — Regulated output voltage |
| 腳位 11 | NC/OUT — Output sense connection (see datasheet) |
| 腳位 12 | PAD — Exposed thermal pad - must be soldered to ground plane |
典型應用
TPS7A84 適用於 6 應用s: FPGA Core and Analog Rail Power, SerDes and Clock Jitter-Sensitive Rails, High-Speed ADC and DAC Analog Supply, Medical Imaging Equipment, Test and Measurement Instrumentation, Video and Broadcast Processing.
FPGA Core and Analog Rail Power
The TPS7A84's 3 A output and 180 mV maximum dropout make it ideal for post-regulating FPGA core and analog rails from nearby switching converters. Its 4.4 uVRMS noise and high PSRR keep power-supply-induced jitter out of FPGA transceiver clocks, while 1% accuracy keeps cores within tight voltage windows. Place the LDO between the DC-DC stage and the FPGA bank with 10 uF low-ESR ceramics; the pin-programmable output from 0.8 V to 3.95 V lets one PCB footprint support multiple voltage banks without feedback resistor changes, simplifying platform BOMs.
推薦
SerDes and Clock Jitter-Sensitive Rails
Power-supply noise directly converts to phase noise and clock jitter in SerDes and PLL circuits. The TPS7A84's 4.4 uVRMS output noise and high PSRR filter upstream buck ripple before it reaches SerDes analog supplies, protecting eye margins in high-speed communications links. TI's datasheet explicitly targets SerDes power with this device. Use the BIAS pin tied to a 3.3 V or 5 V rail so the pass element operates with adequate headroom even from low-VIN rails, and keep the PG output for power-rail sequencing supervision in multi-rail transceiver systems.
推薦
High-Speed ADC and DAC Analog Supply
Precision data converters degrade SNR and SFDR when supply noise couples into reference and analog supply pins. The TPS7A84's 1% output accuracy over line, load, and temperature keeps converter headroom stable, while 4.4 uVRMS noise preserves noise floor. Post-regulate a 5 V or 3.3 V switching rail down to the converter AVDD pin, adding 0.1 uF high-frequency bypass at each supply pin. The thermal pad supports 3 A delivery for multi-channel converters, and current limit plus thermal shutdown protect expensive converters during fault conditions.
推薦
Medical Imaging Equipment
Medical imaging front ends - ultrasound beamformers, CT detector channels - combine high current with extreme noise sensitivity. The TPS7A84 supplies up to 3 A with ultra-low output noise, keeping supply artifacts out of weak receive-chain signals, and its 1% accuracy supports precise biasing of analog front-end ICs. TI's product page lists medical as a target market. Industrial-grade thermal management with the exposed-pad VQFN-20 handles continuous imaging duty cycles; the power-good output enables safe startup sequencing for patient-safety interlocked subsystems.
推薦
Test and Measurement Instrumentation
Oscilloscope front ends, signal generators, and spectrum analyzers demand rails with minimal phase-noise contribution. The TPS7A84 limits power-supply-generated phase noise per TI documentation, making it suitable for oscillator and synthesizer supplies in bench instruments. Its pin-programmable outputs (0.8 V to 3.95 V) let a single PCB design serve multiple instrument variants, cutting qualification cost. Use low-ESR ceramic capacitors per datasheet recommendations and reserve headroom for the 3 A transient loads typical of pulsed measurement circuitry.
推薦
Video and Broadcast Processing
High-speed video signal chains - HDMI/SDI equalizers, crosspoint switches, video DACs - are sensitive to supply-borne ripple that appears as visible banding or sampling clock jitter. The TPS7A84's combination of 3 A capability and 4.4 uVRMS noise powers several video channel loads from one regulator. TI identifies video as a key application market. Set the output by pin-programming for standard 1.8 V or 3.3 V video rails, and rely on the high PSRR to reject noise from a shared switching supply feeding the whole board.
推薦
推薦產品摘要
工程參考資料，適用於 TPS7A84 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | TPS7A84A | TPS7A8300QRGRRQ1 | TPS74401 | TPS7A88 |
|---|---|---|---|---|---|
| Package | VQFN-20 (RGR) | VQFN-20 (RGR) - same | VQFN-20 (RGR) - same | VQFN-20 - same footprint | VQFN-20 - same family |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Output Current | 3 A | 3 A | 3 A | 3.5 A | 3 A per channel (dual) |
| Automotive Grade (AEC-Q100) | No | No | Yes (Q1) | No | No |
| Power Good Output | Yes | Yes | Yes (PGOOD) | Yes (PGOOD) | Yes |
主要差異化特點
- Pin-programmable output without feedback resistors (對比TPS74401)
- Best-in-class 4.4 uVRMS noise at 3 A (對比TPS7A8300QRGRRQ1)
- 180 mV maximum dropout at 3 A (對比TPS7A84A)
設計說明
At 3 A load, dissipation equals (VIN - VOUT) x 3 A. With 2.5 V dropout that is 7.5 W - far beyond what the VQFN-20 theta-JA allows without heavy thermal management. Best practice is to post-regulate from a switcher set 300-500 mV above the LDO output. Solder the exposed pad to at least 1 square inch of 2 oz copper with an array of thermal vias; without it, full 3 A delivery is not achievable.
Place 10 uF low-ESR ceramic capacitors at IN and OUT as close to the pins as possible, with 0.1 uF in parallel for high-frequency bypass per TI datasheet recommendations. Use Kelvin connections for the FB sense trace so it does not carry load current. Connect BIAS to a stable higher rail (3.3 V or 5 V) when VIN is near the output to guarantee headroom for internal circuitry.
Do not exceed the 6.5 V maximum input. If using the adjustable mode, set FB divider current low but not so low that leakage dominates; 1% resistors preserve the 1% output accuracy. When migrating to TPS7A84A, verify power-good polarity and startup behavior in your sequencing scheme - performance improvements can slightly shift timing. Avoid omitting the PG pull-up resistor.
合規資訊
Compliance details not present in provided web data; consult TI product page quality data for RoHS/REACH certificates.
