AMD

XC2C384-7TQ144C - 9K Gate 1.8V CPLD TQFP-144 | AMD/Xilinx

Name: XC2C384-7TQ144C - 9K Gate 1.8V CPLD TQFP-144 | AMD/Xilinx
Brand: AMD
SKU: XC2C384-7TQ144C

MPN： XC2C384-7TQ144C ✓ 啟用中

1.8 V Vdss 14 uA Id 144-pin TQFP (TQ144) Package 217 MHz Speed

索取報價

MOQ： 1 |

查看資料表 (PDF) 查看替代品

數量

XC2C384-7TQ144C 概覽

The AMD (Xilinx) XC2C384-7TQ144C is a CoolRunner-II family CPLD (complex programmable logic device) with 9K system gates, 384 macro cells, a 7.1 ns pin-to-pin propagation delay and 14 uA quiescent current, housed in a 144-pin TQFP (TQ144) surface-mount package rated 0C to +70C.

A CPLD is a class of programmable logic device that sits between SPLDs (such as GAL/PAL devices) and FPGAs in the programmable-logic hierarchy. CPLDs use a macro-cell-based architecture with a deterministic, fully-connected programmable interconnect, which means every signal path has a fixed, predictable delay. This makes CPLDs the preferred choice for glue logic, state machines, bus interfacing, power-up sequencing and address decoding, where pin-to-pin timing consistency matters more than raw gate count.

Key features of the XC2C384-7TQ144C include its 1.8V supply optimization, which dramatically lowers dynamic power compared to 3.3V and 5V CPLD families, its 0.18-micron CMOS process that yields the industry-fastest 7.1 ns pin-to-pin delays for a low-power CPLD, and an ultra-low 14 uA quiescent current that suits battery-powered and always-on designs. The device offers up to 240 user I/O pins, giving designers extensive pin availability in a 0.5 mm-pitch 144-lead TQFP footprint.

Architecturally, CoolRunner-II macro cells combine a programmable AND/OR logic array with configurable registers, supporting combinational and sequential functions per cell. The family is programmed via industry-standard JTAG and is supported by the AMD/Xilinx ISE design suite for synthesis, fitting and in-system programming.

Typical applications include bus-interface translation and control, microprocessor glue logic, industrial control sequencing, communications line-card management and replacing multiple discrete logic devices to reduce board area and BOM count.

For design, note that 1.8V I/O standards apply - confirm level compatibility with 3.3V host devices before committing the board, and follow the manufacturer datasheet for JTAG programming-chain requirements.

This page synthesizes distributor availability data, drop-in family alternatives, comparison tables and practical design notes not found in the manufacturer datasheet alone.

直接替換替代品，適用於 XC2C384-7TQ144C — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。

此系列的變體

與下列產品可直接替換的同系列型號： XC2C384-7TQ144C （相同外形與佔位） — 差異在於 Package.

XC2C256-7TQG144C

AMD

Package: 144-pin TQFP

比較對象 XC2C384-7TQ144C →

XC2C384-10TQG144C

✅ 直接替換

📦 144-pin TQFP (TQ144)

same die and TQ144 footprint, slower -10 speed grade: 10 ns vs 7.1 ns pin-to-pin delay (-29% speed), lead-free G finish

📋 參考替代品（不在目錄中）

XC2C384-7TQG144C

✅ 直接替換

📦 144-pin TQFP (TQ144)

same die, speed grade and package; lead-free/RoHS (G) finish instead of standard finish

📋 參考替代品（不在目錄中）

XC2C256-7TQG144C

✅ 直接替換 ⚠️ 規格未經驗證

AMD

📦 144-pin TQFP (TQ144)

Complex Programmable Logic Device (CPLD) · CoolRunner-II · 256 macrocells · 16 · 6.7 ns · 152 MHz · 6000 gates · 118

聯絡詢價

查看資料表 →

XC2C512-7TQ144C

✅ 直接替換 ⚠️ 規格未經驗證

📦 144-pin TQFP (TQ144)

same TQ144 footprint and -7 speed grade, higher density: 512 vs 384 macro cells (+33% logic capacity)

📋 參考替代品（不在目錄中）

XC2C384-7TQ144C 最大額定值與電氣特性

Family	CoolRunner-II
System Gates	9K gates
Macro Cells	384
User I/O	240 pins
Pin-to-Pin Delay	7.1 ns
Maximum Toggle Frequency	217 MHz
Process Technology	0.18 um CMOS
供應電壓	1.8 V
靜態電流	14 uA
Logic Family	CMOS
封裝	144-pin TQFP (TQ144)
安裝類型	Surface Mount
工作溫度	0 to +70 C
Programming Method	JTAG in-system programmable
Speed Grade	-7
Temperature Grade	Commercial (C)

XC2C384-7TQ144C 144-pin tqfp (tq144) 腳位配置指南

XC2C384-7TQ144C（144-pin tqfp (tq144) 封裝）的腳位配置。此數位 IC 包含 GPIO、通訊介面（UART、SPI、I2C）與電源腳位。替代腳位功能與配置選項請參閱製造商資料表。對嵌入式系統設計與 PCB 佈局至關重要。

XC2C384-7TQ144C 的 144-pin tqfp (tq144) 封裝腳位圖

無詳細腳位定義資料： XC2C384-7TQ144C.

請參閱資料表以查看完整腳位配置。

典型應用

XC2C384-7TQ144C 適用於 6 應用s: Microprocessor Glue Logic, Bus Interface Translation and Control, Industrial Control Sequencing, Power-Up Sequencing and Reset Management, Communications Line-Card Logic, Discrete Logic Consolidation.

🖥️

Microprocessor Glue Logic

The XC2C384-7TQ144C consolidates address decoding, chip-select generation, read/write control and wait-state logic around embedded processors into one 384-macro-cell device. Its deterministic 7.1 ns pin-to-pin delay guarantees that decode timing is identical on every path, which is essential when memory chips have tight access-window requirements. Running from 1.8 V with 14 uA quiescent current, it replaces dozens of 74-series devices, cutting board area and BOM count while improving reliability. With 240 user I/Os in TQ144, wide 16-bit and 32-bit buses can be managed from a single package, and JTAG in-system programming lets control logic be updated during manufacturing or field service without board rework.

推薦

🌐

Bus Interface Translation and Control

Bridging legacy 3.3V or 5V buses to modern 1.8V logic is a classic CoolRunner-II task. The XC2C384-7TQ144C implements bidirectional transceivers, direction latches, byte-swap logic and handshake state machines across its 240 user I/O pins. The 217 MHz toggle capability supports fast synchronous buses, while deterministic macro-cell timing lets designers certify setup and hold margins analytically rather than through timing closure iterations. Low 1.8 V core operation keeps interface power low, important in dense line cards. Because configuration is retained through power cycles with instant-on operation, the interface is active immediately at system reset, satisfying host controllers that sample the bus early in boot.

推薦

SP3232EET-L/TR · MaxLinear KSZ8721SL-TR · Microchip Technology

🏭

Industrial Control Sequencing

In industrial automation panels, the XC2C384-7TQ144C executes deterministic sequencing of actuators, interlocks and safety handshake logic. The CPLD architecture provides fixed 7.1 ns pin-to-pin delays, so state transitions occur with predictable timing regardless of logic placement - a property relay replacements and microcontroller software loops cannot guarantee. The commercial 0 to +70 C rating covers standard cabinet environments, and the 1.8 V supply with 14 uA standby supports always-on monitoring functions. JTAG field reprogramming allows sequence changes to be applied during maintenance windows. Designers typically pair the CPLD with a supervisory device to enforce clean power-up of the sequencing logic.

推薦

MSP430F5519IPN · Texas Instruments PCA9534DWR · Texas Instruments

⚡

Power-Up Sequencing and Reset Management

Multi-rail systems need ordered power-up: the XC2C384-7TQ144C monitors supply-good signals and gates enable outputs in the required order with hard-wired deterministic timing. Its instant-on flash-backed configuration means the sequencing logic is live within nanoseconds of power arrival - no configuration download delay as with SRAM FPGAs. With 384 macro cells, designers can encode multiple sequencing profiles selected by board strapping options. Quiescent current of 14 uA keeps the sequencing function invisible to overall standby power budgets in battery and energy-harvesting equipment. Output enables can also implement hot-swap and brownout hold-off behavior across the 240 available I/O pins.

推薦

MSP430L092SPWR · Texas Instruments TUSB2551PWR · Texas Instruments

📡

Communications Line-Card Logic

Telecom and datacom line cards use the XC2C384-7TQ144C for frame-sync generation, HDLC-like framing assist, LED/status multiplexing and slot-address decoding across backplane connectors. The 217 MHz family toggle rate and 7.1 ns pin-to-pin delay comfortably handle 8-bit parallel control buses at standard line-card clock rates, while deterministic timing simplifies timing-budget sign-off across a multi-vendor card set. The 240 user I/Os of the TQ144 package interface to backplane connectors, front-panel indicators and serial transceivers simultaneously. Low 1.8 V operation reduces per-card power, an important metric when cards are deployed in hundreds-of-slot shelves.

推薦

CS4223-KSR · Cirrus Logic Inc. CS8427-CSR · Cirrus Logic Inc.

🔧

Discrete Logic Consolidation

A frequent redesign driver: replacing 30-60 TTL/CMOS SSI/MSI packages (counters, latches, decoders, comparators) with one XC2C384-7TQ144C. The 384 macro cells provide ample capacity, and the 0.18 um CMOS process keeps power far below bipolar-era discrete logic despite higher integration. Board area shrinks dramatically, assembly cost drops, and reliability improves because inter-chip failures disappear. Deterministic delays often make consolidated designs faster than the original discrete chain. Because the TQ144 footprint is shared across CoolRunner-II densities (XC2C256/XC2C384/XC2C512), a consolidation design can migrate density later without PCB respin - a meaningful hedge against scope growth.

推薦

CD4052BPW · Texas Instruments LM339PWR · Texas Instruments

推薦產品摘要

MC9S08SE8CTG NXP Semiconductors 用於： Microprocessor Glue Logic ATXMEGA64A1-CUR Microchip Technology 用於： Microprocessor Glue Logic SP3232EET-L/TR MaxLinear 用於： Bus Interface Translation and Control KSZ8721SL-TR Microchip Technology 用於： Bus Interface Translation and Control MSP430F5519IPN Texas Instruments 用於： Industrial Control Sequencing PCA9534DWR Texas Instruments 用於： Industrial Control Sequencing MSP430L092SPWR Texas Instruments 用於： Power-Up Sequencing and Reset Management TUSB2551PWR Texas Instruments 用於： Power-Up Sequencing and Reset Management CS4223-KSR Cirrus Logic Inc. 用於： Communications Line-Card Logic CS8427-CSR Cirrus Logic Inc. 用於： Communications Line-Card Logic CD4052BPW Texas Instruments 用於： Discrete Logic Consolidation LM339PWR Texas Instruments 用於： Discrete Logic Consolidation

What is XC2C384-7TQ144C?

XC2C384-7TQ144C is an AMD (formerly Xilinx) CoolRunner-II CPLD with 9K system gates, 384 macro cells and up to 240 user I/O pins in a 144-pin TQFP package. It operates from a single 1.8 V supply, delivers 7.1 ns pin-to-pin delays at up to 217 MHz, and draws only 14 uA quiescent current. According to the manufacturer datasheet, it targets low-power glue logic, bus interfacing and control-sequencing applications in the 0 to +70 C commercial temperature range.

What is the supply voltage of the XC2C384-7TQ144C?

The XC2C384-7TQ144C operates from a single 1.8 V supply. According to the manufacturer datasheet, the CoolRunner-II family was optimized specifically for 1.8 V systems, and the 0.18 um CMOS process keeps quiescent current as low as 14 uA. Designers interfacing with 3.3V devices must verify I/O standard compatibility and level-shifting requirements, since the core supply and nominal I/O operation are specified for 1.8 V rails.

What package does XC2C384-7TQ144C use and what is the footprint?

The XC2C384-7TQ144C is housed in a 144-lead Thin Quad Flat Pack (TQFP, package code TQ144), a 0.5 mm-pitch gull-wing surface-mount package. Other CoolRunner-II density options were also offered in this same TQ144 footprint (for example XC2C256 and XC2C512 devices with the TQ144 suffix), which share the same land pattern. Always confirm pinout and density mapping against the manufacturer datasheet pin tables before reusing a footprint across densities.

How fast is the XC2C384-7TQ144C - what is the pin-to-pin delay?

The XC2C384-7TQ144C in the -7 speed grade offers a 7.1 ns pin-to-pin propagation delay, the fastest grade of the CoolRunner-II family, with operation up to 217 MHz. Because CoolRunner-II uses a deterministic macro-cell and interconnect architecture, these delays are predictable regardless of the routing chosen, unlike FPGA designs where timing depends on place-and-route. This makes the device well suited to decode logic and bus arbitration with tight, known timing windows.

What is the difference between XC2C384-7TQ144C and XC2C384-10TQG144C?

The two devices share the same CoolRunner-II die, 384 macro cells and TQ144 footprint; the difference is speed grade and lead finish/temperature coding. The XC2C384-7TQ144C is the -7 speed grade with a 7.1 ns pin-to-pin delay in a standard commercial part, while the XC2C384-10TQG144C is the -10 grade with a 10 ns pin-to-pin delay and RoHS-compliant lead-free (G) finish. Designs meeting timing at 10 ns can generally use either, but the -7 grade provides timing margin.

Can XC2C256-7TQG144C replace XC2C384-7TQ144C?

Only if your design uses 256 or fewer macro cells. The XC2C256-7TQG144C is a smaller CoolRunner-II device in the same TQ144 package family, so the physical footprint is shared, but the -7TQ144C offers 384 macro cells versus 256. If the implemented design fits in 256 macro cells and the pinout mapping is compatible, the fit is possible; otherwise re-fit the design or choose the XC2C512-7TQ144C for more headroom. Always re-run the ISE fitter and verify pin assignments before substitution.

When should I choose the XC2C384-7TQ144C over an FPGA?

Choose the XC2C384-7TQ144C when you need deterministic 7.1 ns pin-to-pin timing, ultra-low 14 uA standby current, instant power-up operation and non-volatile-style configuration retention without a configuration PROM. FPGAs are better for large datapaths, memory blocks and DSP. For glue logic, state machines, bus control and power sequencing with 384 macro cells or fewer, the CPLD is simpler to design, boots instantly and consumes far less standby power than a typical SRAM FPGA.

Is the XC2C384-7TQ144C suitable for battery-powered designs?

Yes. With a quiescent current of only 14 uA and a 1.8 V supply, the XC2C384-7TQ144C is among the lowest-power programmable logic devices available, and the CoolRunner-II family was explicitly optimized for low power. Dynamic power scales with switching activity and frequency (up to 217 MHz), so battery designs should keep toggle rates modest. Compared with SRAM FPGAs that draw milliamperes of standby current, this CPLD extends battery life dramatically in always-on control functions.

What is the best drop-in replacement for XC2C384-7TQ144C?

The closest drop-in option within the same family is XC2C384-10TQG144C, which shares the identical die, 384 macro cells and TQ144 footprint with only a slower speed grade (10 ns versus 7.1 ns pin-to-pin). It is lead-free/RoHS coded. If your static timing analysis closes at 10 ns, this is a direct replacement. Within the wider CoolRunner-II TQ144 family, XC2C256 and XC2C512 devices cover lower and higher densities on the same package outline. No cross-brand pin-compatible equivalent is documented in manufacturer cross-reference data.

What is the best AMD/Xilinx equivalent in the CoolRunner-II family for XC2C384-7TQ144C?

Within AMD/Xilinx's own CoolRunner-II family, the XC2C384-10TQG144C is the nearest equivalent (same die, same TQ144 package, slower -10 speed grade), and the XC2C384-7TQG144C is the same speed grade with lead-free finish. For more logic headroom on the same footprint, the XC2C512-7TQ144C offers 512 macro cells in TQ144. No cross-brand vendor offers a documented pin-compatible CoolRunner-II equivalent, so family-internal substitution is the recommended strategy.

Where can I download the XC2C384-7TQ144C datasheet PDF?

The manufacturer datasheet for the XC2C384-7TQ144C is available for download from the product page on this site via the datasheet link, and from AMD/Xilinx official documentation resources covering the CoolRunner-II family (the family datasheet covers package pinouts, DC/AC parameters and JTAG programming). Use the pin-description tables in the CoolRunner-II family datasheet when assigning I/O pins, and the package drawings section for the TQ144 mechanical footprint.

How do I program the XC2C384-7TQ144C?

The XC2C384-7TQ144C is programmed in-system via its JTAG port using the AMD/Xilinx ISE design suite together with a Platform Cable or compatible JTAG programmer. The flow is: synthesize the design, fit it to the 384 macro cells with the CoolRunner-II fitter, generate a SVF/JED programming file, and download it over JTAG. CoolRunner-II devices retain configuration on power-down (they are flash-based at the block level), so no external configuration PROM is needed - the device is functional immediately at power-up.

Where can I buy XC2C384-7TQ144C and check stock and lead time?

You can purchase XC2C384-7TQ144C directly through the Request a Quote form on this XAIPART product page. Submit your required quantity and target delivery date, and our sourcing team will respond with current stock, pricing and lead time. Because the CoolRunner-II family has moved to mature status, authorized-channel stock can be limited, so requesting a quote early and specifying full quantity needs is the most reliable way to secure supply for production builds.

What is the price of XC2C384-7TQ144C?

XC2C384-7TQ144C is priced per unit with quantity discounts, and current pricing depends on stock position and order volume. Request an exact quotation through the Request a Quote form on this page - XAIPART will return unit pricing at your required quantity tiers along with lead time and shipping terms. This ensures you receive today's live price rather than a stale published figure, which matters for mature programmable-logic devices where channel stock changes frequently.

What are the key specifications of XC2C384-7TQ144C that engineers should know?

The essential facts: it is an AMD/Xilinx CoolRunner-II CPLD with 9K system gates and 384 macro cells; it provides up to 240 user I/O pins in a 144-lead TQFP (TQ144) package; supply voltage is 1.8 V with 14 uA quiescent current; the -7 speed grade delivers 7.1 ns pin-to-pin delay at up to 217 MHz on a 0.18 um CMOS process; operating temperature is 0 to +70 C; and programming is via JTAG using the Xilinx ISE toolchain. These figures come from the manufacturer datasheet.

工程參考資料，適用於 XC2C384-7TQ144C — 比較、設計指引及合規資訊。

選型指南

Choose the XC2C384-7TQ144C when a low-power 1.8 V design needs roughly 300-380 macro cells with the fastest 7.1 ns deterministic pin-to-pin timing and 240 user I/Os in a TQ144 footprint. If your static timing closes at 10 ns, the XC2C384-10TQG144C offers the identical die with more relaxed timing and lead-free finish - usually the safer procurement choice for new RoHS builds. Choose XC2C256-7TQG144C when the fitted design stays well under 256 macro cells and cost dominates. Choose XC2C512-7TQ144C when logic growth is likely or decode chains are wide. All four share the TQ144 land pattern, so density migration avoids board respin. Against an FPGA: choose this CPLD for instant-on operation, 14 uA standby, fixed timing and no configuration PROM; choose an FPGA only when you need RAM blocks, DSP slices or thousands of gates.

與替代品比較

參數	本產品	XC2C384-10TQG144C	XC2C384-7TQG144C	XC2C256-7TQG144C	XC2C512-7TQ144C
Brand	AMD (Xilinx)	AMD (Xilinx)	AMD (Xilinx)	AMD (Xilinx)	AMD (Xilinx)
Package	144-pin TQFP (TQ144)	144-pin TQFP (TQ144) - same	144-pin TQFP (TQ144) - same	144-pin TQFP (TQ144) - same	144-pin TQFP (TQ144) - same
Macro Cells	384	384	384	256	512
Pin-to-Pin Delay	7.1 ns	10 ns	7.1 ns	7.1 ns	7.1 ns
Supply Voltage	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
Operating Temperature	0 to +70 C	0 to +70 C	0 to +70 C	0 to +70 C	0 to +70 C
Lead Finish	Standard (C suffix)	Lead-free (G suffix)	Lead-free (G suffix)	Lead-free (G suffix)	Standard (C suffix)

主要差異化特點

Fastest CoolRunner-II speed grade (對比XC2C384-10TQG144C)
Standard-finish commercial coding (對比XC2C384-7TQG144C)
Balanced density in the shared TQ144 footprint (對比XC2C256-7TQG144C)

設計說明

The XC2C384-7TQ144C runs from a single 1.8 V rail. Estimate dynamic power as P ≈ C·V²·f·N, where N is the number of simultaneously switching outputs - dynamic power rises quickly with I/O toggle rate and load capacitance, so derate designs toggling many outputs near the 217 MHz family maximum. Decouple with at least 100 nF ceramic per supply pin group plus bulk capacitance per the manufacturer datasheet recommendations, placed within a few millimeters of the pins. The 14 uA quiescent figure applies at standby; power budget reviews must use dynamic estimates for active operation.

The 1.8 V I/O must be level-checked against 3.3 V host devices before finalizing the schematic - most 3.3 V outputs will overdrive 1.8 V inputs beyond recommended limits, so plan series limiting or level translators where rail domains differ. Series source termination (typically 22-33 ohm) on fast outputs driving ribbon cable or long traces will control overshoot and ground bounce. The CoolRunner-II datasheet provides per-drive-strength output impedance; use it when calculating reflection coefficients for your trace geometry.

Two frequent mistakes with CoolRunner-II designs: (1) underestimating macro-cell usage - a 384-macro-cell device may not fit a design that 'looks' small because wide decoders and registered buses consume multiple cells per output; run the ISE fitter early to confirm fit before committing the PCB. (2) Substituting a -10 grade part for the -7 without re-running static timing - the 7.1 ns to 10 ns difference can break marginal decode windows. Also remember the commercial 0 to +70 C rating: extended-temperature designs require the I-grade variant, which has a different ordering code.

合規資訊

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

無鉛

Unknown

無鹵

Unknown

衝突礦產

Unknown

The standard C-suffix part's lead finish and RoHS status were not stated in the retrieved product listings; lead-free G-suffix variants (e.g., XC2C384-7TQG144C) exist in the same family. Request formal compliance certificates through the quote process.

資料驗證日期： 2026-11-08 — 資料由 XAIPART 元件工程團隊驗證及整理

來源： Manufacturer Datasheet, Distributor, Distributor, Octopart, Manufacturer Datasheet, Manufacturer Datasheet