AMD

XC9572-7PQ100C - 72-Macrocell 7.5 ns CPLD | AMD Xilinx

Name: XC9572-7PQ100C - 72-Macrocell 7.5 ns CPLD | AMD Xilinx
Brand: AMD
SKU: XC9572-7PQ100C

MPN： XC9572-7PQ100C ✗ 停產

4.75 V to 5.25 V Vdss 100-pin QFP Package Up to 125 MHz Speed

索取報價

MOQ： 1 |

查看資料表 (PDF) 查看替代品

數量

XC9572-7PQ100C 概覽

AMD Xilinx XC9572-7PQ100C is a 72-macrocell, 5 V in-system programmable complex programmable logic device in a 100-pin QFP package. It provides 72 I/O, 1,600 usable gates, a maximum pin-to-pin delay of 7.5 ns, and a stated fCNT of up to 125 MHz. The device uses Advanced CMOS 5V FastFLASHTM technology, supports parallel programming of multiple XC9500 devices, and provides at least 10,000 program/erase cycles.

A CPLD is a configurable logic device that combines macrocell-based programmable logic, user-programmable interconnect, and nonvolatile configuration memory. Within the product hierarchy, the XC9572-7PQ100C is a CPLD, a member of the XC9500 programmable logic family, and a 5 V logic semiconductor intended for general-purpose logic integration. Its in-system programmability permits configuration through the assembled PCB rather than requiring a separate programming operation before insertion.

Key features include 72 macrocells, 72 I/O, four function blocks, 1,600 gates, and pin-to-pin logic delays specified down to 7.5 ns for this speed grade. The flexible 36V18 function block allows 90 product terms to drive any or all 18 macrocells within each block. The device also supports enhanced pin locking and programming over the full commercial voltage and temperature range.

The Advanced CMOS 5V FastFLASHTM architecture provides a practical combination of nonvolatile configuration storage, predictable logic performance, and repeatable in-system programming. A system designer can use the CPLD for interface translation, control logic, bus arbitration, state-machine implementation, glue logic, and prototype logic consolidation. The 100-pin package provides more I/O than smaller XC9500 packages while retaining a conventional surface-mount form factor.

Typical applications include industrial control systems, instrumentation interfaces, communications equipment, test and measurement products, and embedded control platforms. It is particularly useful when a design requires frequent field updates, nonvolatile configuration retention, or a compact replacement for multiple individually packaged logic elements.

When designing around the XC9572-7PQ100C, verify the 4.75 V to 5.25 V internal supply range, respect the commercial temperature and timing limits, and confirm the exact 100-pin footprint and signal assignments against the manufacturer datasheet. Programming-file generation and device programming must also use tools supporting the legacy XC9500 architecture.

直接替換替代品，適用於 XC9572-7PQ100C — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。

XC9572-10PQ100C

✅ 直接替換 ⚠️ 規格未經驗證

📦 100-pin QFP (PQ100)

Same XC9572 capacity and PQ100 package, but the -10 speed grade is slower than the target's 7.5 ns maximum pin-to-pin delay; timing margin decreases by approximately 25%.

📋 參考替代品（不在目錄中）

XC9572-6PQ100C

✅ 直接替換 ⚠️ 規格未經驗證

📦 100-pin QFP (PQ100)

Same XC9572 capacity and PQ100 package, but the -6 speed grade has a nominal 6 ns class rather than the target's 7.5 ns maximum delay, improving timing by approximately 20%.

📋 參考替代品（不在目錄中）

XC9572-5PQ100C

✅ 直接替換 ⚠️ 規格未經驗證

📦 100-pin QFP (PQ100)

Same XC9572 capacity and PQ100 package, but the -5 speed grade is faster than the target's 7.5 ns maximum delay, providing approximately 33% lower nominal delay.

📋 參考替代品（不在目錄中）

XC9572-7PQ100I

✅ 直接替換 ⚠️ 規格未經驗證

📦 100-pin QFP (PQ100)

Same XC9572 density, -7 timing grade, and PQ100 package, but the I suffix denotes the industrial temperature option rather than the target's commercial grade.

📋 參考替代品（不在目錄中）

XC9572XL-7TQG100C

✅ 直接替換

📦 100-pin QFP (TQG100)

Documented same-density 100-pin QFP candidate with a 7 ns speed grade; the XL architecture, electrical characteristics, timing, and programming-file compatibility differ from the legacy 5 V XC9572 and require migration verification.

📋 參考替代品（不在目錄中）

XC9572-7PQ100C 最大額定值與電氣特性

Device Type	Complex Programmable Logic Device (CPLD)
Family	XC9500
Number of Macrocells	72 macrocells
Number of I/O	72 I/O
Number of Function Blocks	4 function blocks
Number of Gates	1,600 gates
Maximum Pin-to-Pin Delay	7.5 ns
Counter Frequency	Up to 125 MHz
Internal Supply Voltage	4.75 V to 5.25 V
Programming Type	In-system programmable
Program/Erase Endurance	Minimum 10,000 cycles
Configuration Technology	Advanced CMOS 5V FastFLASHTM
封裝	100-pin QFP
Number of Terminals	100 terminals
Temperature Grade	Commercial
Lead-Free Status	Contains lead
RoHS 狀態	RoHS non-compliant
Product Status	Obsolete
Pin-Locking Support	Enhanced pin-locking architecture
Parallel Programming	Supported for multiple XC9500 devices
Product Terms per Function Block	90 product terms drive any or all 18 macrocells

XC9572-7PQ100C 100-pin qfp 腳位配置指南

XC9572-7PQ100C（100-pin qfp 封裝）的腳位配置。此數位 IC 包含 GPIO、通訊介面（UART、SPI、I2C）與電源腳位。替代腳位功能與配置選項請參閱製造商資料表。對嵌入式系統設計與 PCB 佈局至關重要。

無詳細腳位定義資料： XC9572-7PQ100C.

請參閱資料表以查看完整腳位配置。

典型應用

XC9572-7PQ100C 適用於 6 應用s: Industrial Control and Automation Logic, Test and Measurement Instrument Control, Communication Interface Consolidation, Embedded Control Platform, Programmable Signal Conditioning, Legacy System Consolidation.

🏭

Industrial Control and Automation Logic

The XC9572-7PQ100C fits industrial control boards that require deterministic programmable logic close to sensors, actuators, and communication transceivers. Its 72 macrocells and 72 I/O can consolidate state machines, interlocks, level translation, and bus-control functions that would otherwise occupy multiple discrete logic devices. The listed 7.5 ns maximum pin-to-pin delay supports timing-sensitive control paths, while in-system programming allows firmware updates without removing the device. Because the verified part is commercial grade and RoHS non-compliant, the final design must confirm the ambient-temperature range, lifecycle status, and environmental-policy requirements.

推薦

🔧

Test and Measurement Instrument Control

The XC9572-7PQ100C is appropriate for instrument-control logic that coordinates triggers, mode selection, status indicators, and data-path switching. Its four function blocks and 1,600 usable gates provide enough capacity for multiple small state machines, while 72 I/O support instrument-panel and motherboard signal distribution. The 7.5 ns timing class can reduce uncertainty in synchronous control paths compared with the slower -10 grade. In-system programming is valuable for laboratory equipment because trigger and interface behavior can be revised during development without desoldering the CPLD.

推薦

PCA9517DR · Texas Instruments ATMEGA2560-16AUR · Microchip Technology TUSB2036VF · Texas Instruments

🌐

Communication Interface Consolidation

The XC9572-7PQ100C can consolidate protocol adapters, FIFO control logic, baud-rate selection, and signal isolation between legacy and modern communication blocks. Its 72 I/O and 72 macrocells are useful for parallel-to-serial boundary logic and asynchronous handshake control, while the 100-pin QFP package offers enough external connections for multiple bus segments. The 125 MHz family fCNT figure should not be confused with a guaranteed 125 MHz I/O data rate; designers must use the actual timing constraints and board-level signal-integrity analysis to establish achievable throughput.

推薦

LAN8742A-CZ · Microchip Technology CP2102N-A01-GQFN20R · Silicon Labs MAX202IDR · Texas Instruments

🧩

Embedded Control Platform

The XC9572-7PQ100C fits embedded platforms where a microcontroller requires dedicated hardware for boot control, watchdog handling, interrupt routing, or peripheral arbitration. Programmable nonvolatile storage allows the logic design to remain after power removal, and in-system programming supports controlled field updates. With 1,600 gates and 72 macrocells, the device is best suited to glue logic rather than a processor-intensive workload. A design should reserve enough pins for configuration access and verify that the CPLD's 5 V supply requirements coexist with the selected microcontroller and transceiver voltage levels.

推薦

ATMEGA328P-MNR · Microchip Technology STM32F429NIH6TR · STMicroelectronics TCA4311DR · Texas Instruments

📺

Programmable Signal Conditioning

The XC9572-7PQ100C can implement programmable pulse shaping, edge conditioning, alarm masking, and signal-routing logic in acquisition or control equipment. Its 72 macrocells allow several independent finite-state functions to operate concurrently, while the 7.5 ns grade supports short combinational paths and registered timing constraints. The in-system programming capability permits adjustment of thresholds and routing behavior without changing the PCB. Signal-integrity performance still depends on external buffers, termination, grounding, and trace geometry; the CPLD cannot compensate for poorly implemented high-speed physical layers.

推薦

ADV7311KST · Analog Devices ADV7202KST · Analog Devices NE5534DR · Texas Instruments

🖥️

Legacy System Consolidation

The XC9572-7PQ100C is useful when replacing several PAL, GAL, or small discrete-logic devices in an older system while retaining a 5 V architecture. Its 72 macrocells can absorb address decoding, latch control, interrupt qualification, and miscellaneous state logic, reducing board area and assembly cost. The 100-pin QFP package provides more I/O than smaller CPLD options, and in-system programming supports consolidation during maintenance. The replacement plan must include a complete pin-by-pin comparison, a migration of the existing logic equations, and verification of legacy timing behavior.

推薦

L9678P · STMicroelectronics MC1458D · Texas Instruments MAX232DR · Texas Instruments

推薦產品摘要

What are the key specifications of XC9572-7PQ100C that engineers should know?

The XC9572-7PQ100C is a 72-macrocell CPLD with 72 I/O, four function blocks, 1,600 gates, and a 100-pin QFP package. According to the AMD Xilinx DS065 data sheet, the -7 grade offers a 7.5 ns maximum pin-to-pin delay, while the family supports fCNT up to 125 MHz. It operates from a 4.75 V to 5.25 V internal supply and uses in-system programmable nonvolatile FastFLASHTM configuration.

Where can I download the XC9572-7PQ100C datasheet PDF?

The official XC9572-7PQ100C data sheet is available from AMD at https://docs.amd.com/v/u/en-US/ds065. The page identifies the document as DS065, with a release date of 2013-05-17 and revision 5.0. It covers the XC9572 in-system programmable CPLD and should be used as the primary reference for timing, pin assignments, electrical characteristics, and programming information.

Where can I find the XC9572-7PQ100C pinout?

The XC9572-7PQ100C pinout is documented in the official AMD Xilinx DS065 data sheet at https://docs.amd.com/v/u/en-US/ds065. The exact signal assignments should be verified against the 100-pin PQ package drawing before PCB layout or replacement assembly. The supplied web results identify the package and terminal count but do not include a complete verified pin table, so no pin names are reproduced here.

Is XC9572-7PQ100C in stock?

Stock status changes across distributors, so the current inventory should be confirmed before ordering. DigiKey lists the AMD XC9572-7PQ100C with manufacturer part number 122-1173-ND, while the Octopart result compares availability from 24 distributors. The verified data does not provide a current XAIPART stock count or a fixed lead time, so an order should be treated as subject to supplier confirmation.

What is the price of XC9572-7PQ100C?

A defensible unit price cannot be stated from the supplied verified results because no current numerical distributor price is included. DigiKey and Octopart provide live pricing and inventory pages, but their excerpts do not expose a quote suitable for publication. Prices for this obsolete device may vary sharply with quantity, condition, and remaining factory inventory; request a current quotation before committing to a production order.

What is the lead time for XC9572-7PQ100C?

The verified data does not state a guaranteed lead time for the XC9572-7PQ100C. Because the device is listed as obsolete and may be supported only by remaining factory or distributor inventory, procurement timing depends on lot availability rather than a normal new-production schedule. Contact the supplier for the quantity available, date code, condition, and traceability before relying on a stated delivery date.

Where to buy XC9572-7PQ100C online?

The XC9572-7PQ100C can be researched through DigiKey, Octopart, IC-Components, and other listed distributors. DigiKey identifies the part number as 122-1173-ND, while Octopart compares offers from 24 distributors. Because this is an obsolete CPLD, verify authorized-channel provenance, date code, package condition, and programming-file compatibility. Distributor presence alone does not establish that an item is factory-new.

What can replace XC9572-7PQ100C?

The closest documented replacement is the AMD Xilinx XC9572XL-7TQG100C, which appears in the verified cross-reference results and uses a 100-pin QFP designation. Drop-in use still requires confirmation of package dimensions, pinout, timing, voltage, and the XC9500 programming-file format. Older 5 V XC9500 parts are not automatically interchangeable with the XL device despite similar device names.

Is XC9572-7PQ100C the same as XC9572-10PQ100C?

No, the XC9572-10PQ100C is a different speed grade, not an identical part. The target XC9572-7PQ100C has a listed maximum pin-to-pin delay of 7.5 ns, whereas the -10 grade is slower by its speed-grade designation. Both can implement the same general XC9500 logic, but timing closure, power behavior, and system timing budgets must be reassessed when substituting the slower device.

XC9572-7PQ100C vs XC9572-10PQ100C: which is better for timing-critical control?

The XC9572-7PQ100C is better for timing-critical control because its specified maximum pin-to-pin delay is 7.5 ns, while the XC9572-10PQ100C belongs to a slower speed grade. Both provide 72 macrocells and 72 I/O in the XC9500 architecture, so capacity is similar. Choose the -7 part when the external interface timing margin is too small for the -10 grade, after checking the complete timing report.

When should I choose XC9572-7PQ100C over a slower XC9572 grade?

Choose the XC9572-7PQ100C when a design cannot meet external setup and hold requirements with a slower XC9500 grade. Its 7.5 ns maximum pin-to-pin delay is approximately 25% lower than the nominal 10 ns timing associated with the -10 grade. The choice matters only when timing analysis identifies a real constraint; otherwise, the slower grade may offer a better price or availability.

Is XC9572-7PQ100C suitable for industrial control applications?

The XC9572-7PQ100C is suitable for industrial control logic when the system uses a 5 V supply and the required operating-temperature range is verified. The part is marked commercial, not automotive-qualified, and the verified excerpts do not provide its full commercial temperature limits. It is appropriate for non-automotive industrial equipment where in-system programming, 72 I/O, and 7.5 ns pin-to-pin timing satisfy the design.

What are the main differences between XC9572-7PQ100C and XC9572XL-7TQG100C?

The XC9572-7PQ100C is a legacy 5 V XC9500 CPLD, while the XC9572XL-7TQG100C belongs to the XC9500XL family and uses a 100-pin QFP package. The verified excerpts do not establish identical pin assignments, electrical limits, timing, or programming-file compatibility. Treat the XL device as a potential 100-pin replacement candidate, not a guaranteed drop-in, until AMD package and migration documentation confirms every requirement.

How much power does XC9572-7PQ100C dissipate?

A reliable power-dissipation value cannot be calculated from the supplied data because the verified excerpts do not include the target's operating current or the I/O load used in the electrical tables. The device uses a 4.75 V to 5.25 V internal supply, but that voltage range alone is insufficient for a power estimate. Consult DS065 for quiescent and active current, then calculate using the actual supply voltage and measured I/O loading.

Does XC9572-7PQ100C support RoHS-compliant manufacturing?

No, the verified product information marks the XC9572-7PQ100C as RoHS non-compliant and containing lead. It is also an obsolete device, so current RoHS exemptions, legacy-use assumptions, and customer environmental policies should be reviewed before deployment. For a new design with strict substance restrictions, select a currently supported programmable-logic family rather than relying on this legacy part.

工程參考資料，適用於 XC9572-7PQ100C — 比較、設計指引及合規資訊。

選型指南

Choose the XC9572-7PQ100C for a legacy 5 V design that requires 72 macrocells, 72 I/O, in-system programmability, and a 7.5 ns timing class in a 100-pin QFP footprint. Select the XC9572-10PQ100C when its slower timing still satisfies the design and better availability or cost is more important. Consider the XC9572-6PQ100C or XC9572-5PQ100C when extra timing margin is beneficial, after checking price and lifecycle availability. Use the XC9572-7PQ100I when the same commercial-device timing is needed in an industrial temperature environment. The XC9572XL-7TQG100C is a documented same-density 100-pin QFP candidate, but it belongs to a different family generation and therefore requires pinout, timing, electrical, and programming-tool migration checks. Because the target is obsolete and RoHS non-compliant, new production should normally use a currently supported CPLD or FPGA unless maintaining an installed legacy platform is essential.

與替代品比較

參數	本產品	XC9572-10PQ100C	XC9572-6PQ100C	XC9572-5PQ100C	XC9572-7PQ100I	XC9572XL-7TQG100C
Brand	AMD	AMD	AMD	AMD	AMD	AMD
Package	100-pin QFP (PQ100)	100-pin QFP (PQ100) - same package	100-pin QFP (PQ100) - same package	100-pin QFP (PQ100) - same package	100-pin QFP (PQ100) - same package	100-pin QFP (TQG100) - same 100-pin QFP class
Macrocells	72 macrocells	72 macrocells	72 macrocells	72 macrocells	72 macrocells	72 macrocells
Maximum Pin-to-Pin Delay	7.5 ns	10 ns class	6 ns class	5 ns class	7.5 ns	7 ns grade
Programming Type	In-system programmable	In-system programmable	In-system programmable	In-system programmable	In-system programmable	In-system programmable

主要差異化特點

Faster timing class than the XC9572-10PQ100C (對比XC9572-10PQ100C)
Commercial-grade option with 7.5 ns timing (對比XC9572-7PQ100I)
Lower nominal delay than the target (對比XC9572-5PQ100C)
Documented 100-pin replacement path within the expanded XC9500 family (對比XC9572XL-7TQG100C)

設計說明

Do not treat all XC9572 speed grades or package suffixes as automatically interchangeable. The XC9572-10PQ100C is slower than the target's listed 7.5 ns class, the XC9572-7PQ100I changes the temperature grade, and the XC9572XL-7TQG100C uses a different family generation. Before substitution, compare the DS065 pin tables, supply limits, AC timing, configuration protocol, and programming software support. A matching 100-pin count alone does not prove pin-to-pin compatibility.

The verified data establishes a 4.75 V to 5.25 V internal supply range but does not provide the target's quiescent current, active current, or I/O loading tables. Do not estimate production power from supply voltage alone. Obtain the electrical characteristics from DS065, calculate static and dynamic dissipation using the actual output activity factor, and include regulator tolerance, input-voltage variation, and temperature when sizing the 5 V supply.

Place the 5 V and ground distribution network so the CPLD has a low-impedance return path. Keep configuration-related traces away from sensitive analog or high-speed switching nodes, and verify every 100-pin footprint dimension and pin-1 orientation against the official package drawing. The verified excerpts do not provide the complete pin table, so the PCB library must be cross-checked directly against DS065 rather than inferred from a generic QFP-100 symbol.

The XC9572 is a legacy XC9500 device, so current software support and configuration-file compatibility may be more important than raw logic capacity. Confirm that the selected design tool can compile for the correct device speed grade and package suffix, that the programmer supports nonvolatile in-system programming, and that a recoverable configuration method exists. A successful JEDEC file conversion does not by itself prove that all boundary-scan, test, or security features behave identically.

合規資訊

RoHS

Non Compliant

REACH

Unknown

AEC-Q100

Not Applicable

無鉛

無鹵

Unknown

衝突礦產

Unknown

The verified product data states that XC9572-7PQ100C contains lead and is RoHS non-compliant. No verified REACH, halogen-free, conflict-minerals, or automotive-qualification data was supplied. The part is commercial grade and listed as obsolete.

資料驗證日期： 2026-10-29 — 資料由 XAIPART 元件工程團隊驗證及整理

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