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Saras Micro Devices基板内嵌无源器件对AI加速器供电意味着什么

Saras Micro Devices的STILE模块将去耦电容移入封装基板，以缩短VRM到负载的路径，并为AI加速器的垂直供电释放PCB底面空间。

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TL;DR——三句话

  • Saras Micro Devices' STILE technology embeds capacitors into the IC package substrate or PCB, freeing the board underside for vertical power delivery. (S1)
  • AI accelerator TDP is at multiple kilowatts with core voltages of 0.6-0.8 V, so PDN current and resistive losses are rising sharply. (S1)
  • STILE capacitors use 3D pass-through copper terminations, are rated for 125°C operation and reportedly show almost no derating under temperature and bias. (S1)

摘自 key_takeaways （真实字段，最多 3 条）。事实与分析分别标注。

Saras Micro Devices基板内嵌无源器件对AI加速器供电意味着什么 — Semiconductor News news briefEditorial cover for a Semiconductor News brief. Chip motif; headline "Saras Micro Devices基板内嵌无源器件对AI加速器供电意味着什么". Reported key numbers: 12 V. 1 cited source. Static cover (no animation).SEMICONDUCTOR NEWS · NEWS BRIEFSaras Micro Devices基板内嵌无源器件对AI加速器供电意味着什么REPORTED KEY NUMBERS12 V1 sourceXAIPART
Cover image generated from data already shown on this page: the category motif, the headline, and reported key numbers. No decorative illustration; no third-party image.

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AI 摘要可能遗漏了其结论的依据。原始预测、受影响料号及所有引用均在本页，均可追溯至来源。

XAIPART 预测

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受影响的料号

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Reported by 3D InCites on 2026-10-06. Summarized and analyzed by XAIPART Editorial.

What happened

Power electronics vendors are racing to deliver voltage regulators that can handle the multi-kilowatt currents required by AI GPUs and HPC accelerators, but the surrounding discrete inductors and capacitors are starting to dominate board real estate and limit performance.S1

The article describes power delivery as a stack of conversion losses from the rack to the die. Most data center racks use a 54-V/48-V backplane; accelerator boards then drop to 12 V through a 48-to-12-V VRM, followed by lateral 12-V-to-POL VRMs around the chip. As chips move to advanced process nodes, core voltages fall to 0.6-0.8 V while thermal design power (TDP) climbs to multiple kilowatts, so the PDN current P/V rises sharply and resistive (I²R) losses grow exponentially with it.S1

Saras Micro Devices' STILE technology integrates capacitors (and, in future generations, inductors) into the IC package substrate or PCB rather than mounting them on the surface. The capacitors are made to match the substrate thickness, use 3D pass-through copper terminations, show almost no capacitance derating under temperature and bias, and are rated for operation at 125°C.S1 Today's STILE parts target output capacitance for VRMs serving extreme transient loads; a higher-frequency generation with both decoupling capacitance and inductance is under development.S1

The article frames STILE as an enabler for vertical power delivery (VPD). Because the underside of today's boards is crowded with surface-mount decoupling capacitors, those parts block the move of VRMs directly under the chip. Embedding passives inside the substrate or PCB frees the underside for VPD and shortens the regulator-to-load path, reducing parasitic resistance and inductance.S1 Shaun Bowers, SVP of Product Management at Saras Micro Devices, expects the PDN to evolve first toward VPD, then toward higher rack and intermediate voltages, and eventually toward integrated voltage regulators (IVRs) inside the package or on the die, with VPD remaining the front-end stage for those IVRs.S1

Key numbers
MetricReported valueSource
Rack backplane voltage54 V / 48 V[S1]
Board-level intermediate rail12 V[S1]
Processor core operating voltage0.6 to 0.8 V[S1]
Thermal design power range citedMultiple kilowatts per device[S1]
Data center power scale citedApproaching gigawatt level[S1]
STILE capacitor operating temperature rating125°C[S1]
Capacitance derating vs temperature/biasReported as almost none[S1]
Higher-frequency STILE generationNot disclosed (under development)[S1]

Background timeline

  1. No prior milestones disclosed by the source.

XAIPART take

Technical impact

Embedding output-stage capacitance directly under the die cuts the loop inductance and resistance between the last VRM stage and the silicon, which is exactly the regime where AI accelerator transients cause the largest voltage excursions. XAIPART analysis Pairing STILE-class parts with a 48-V-to-POL topology lets designers push the first high-frequency conversion step closer to the load, but thermal co-design becomes the gating issue: every part in the PDN now sits inside the package's hot-spot envelope, and CTE mismatch between copper, substrate laminate and the silicon die can dominate warpage at reflow.

Market impact

The bottleneck narrative in this brief is consistent with what hyperscalers have been signaling on 48-V rack architectures and VPD, but the article is one vendor's viewpoint and one interview. XAIPART analysis If substrate-embedded passives reach volume, the displaced surface-mount MLCC and power-inductor lines serving accelerator boards face a structural demand shift, while substrate and PCB manufacturers gain a higher-value embedding step. Sourcing teams should expect STILE-grade parts to remain single-source for at least the next design cycle.

Action

For procurement, request samples and a roadmap from Saras Micro Devices for STILE output-capacitance parts and the higher-frequency capacitor-plus-inductor generation before locking the PDN bill of materials. XAIPART analysis For design, evaluate VPD feasibility jointly with the embedded-passive supplier so the PCB underside is reserved for VRM landing, and add a 125°C derating check, reflow-profile warpage budget and CTE map to the package-level PDN review.

XAIPART Forecast

If a major hyperscaler or accelerator OEM publicly references Saras Micro Devices STILE in a shipping reference design by 2027-09-30, XAIPART expects at least two competing embedded-passive suppliers (existing MLCC or advanced-substrate vendors) to announce competing package-substrate-embedded PDN products within 9 months of that disclosure; otherwise this forecast is wrong. XAIPART analysis

Facts are as reported by the cited source. The design-in, sourcing and forward-looking statements above are XAIPART's analysis, not the source's claims. Uncertainty: this brief rests on a single interview-based article from one vendor (Saras Micro Devices) and one executive; product roadmap, volume, pricing and customer adoption are not disclosed.

Corrections: none at publication. This brief will be updated with a timestamp if the source corrects its report.

替代料与生命周期

已收录的替代料——仅为目录范围，不代表市场排名
料号关系生命周期依据
— 暂无收录替代料 待补充数据 — 需 match_type 后才可显示任何前代标签

“前代”和“替代”标签仅来自已记录的匹配类型、生命周期状态或来源文本。没有记录匹配时，不显示任何标签。我们自己的商品列表不构成市场参考。

关注要点

可证伪预测——阈值、时间窗口和当前状态。被推翻的预测仍保留可见。
论断阈值发布方状态
If a major hyperscaler or accelerator OEM publicly references Saras Micro Devices STILE in a shipping reference design by 2027-09-30, XAIPART expects at least two competing embedded-passive suppliers (existing MLCC or... a major hyperscaler or accelerator OEM publicly references Saras Micro Devices STILE in a shipping reference design by 2027-09-30, XAIPART expects at least two competing embedded-passive suppliers (existing MLCC or advanced-substrate ven... Pending

被证明错误的预测仍保留可见并加以标注。我们不会删除它们。

竞争格局

  • 22110 个在售商品（XAIPART 此分类）
  • 92 收录制造商
  • 62 家制造商（过去 30 天内出现在我们的新闻存档中）

统计数据仅反映 XAIPART 目录，不代表市场份额。

受影响的料号

目录中无匹配。 此事件未映射到 XAIPART 当前上架的任何料号。我们不推断匹配，也不显示占位列表。

各维度成本压力

Source: FRED · Generated · reference output z and composite are algorithm outputs, not a fetch snapshot

Cost pressure by dimension — composite stateDiverging bars for three dimensions around a zero midpoint. Input Cost has no reading; Supply Demand z -1.4711, notable; Fx Energy z 0.4541, neutral. Composite index -7.6, band neutral.0投入成本no reading供需z −1.4711 · notable46 d汇率与能源z +0.4541 · neutral6 dcomposite −7.6 · neutral−100 · −40 · −15 · 0 · +15 · +40 · +100
Underlying values — copyable for verification.
DimensionFRED series IDUnitLagAs of
投入成本PCOPPUSDM, PALUMUSDM, PNICKUSDMUSD/mt96 d
供需PCU334413334413, IPG3344Sindex(1982=100) / index(2017=100)46 d
汇率与能源DEXCHUS, DCOILBRENTEU, DHHNGSPrate / USD/bbl / USD/MMBtu6 d

No free authoritative interface for: gold · silver · rare earth · polysilicon · lithium carbonate · market share — listed rather than approximated.

本文如何生成

过程证据——抓取、来源可靠性检查、模型与校验
本简报的审计记录
Source fetched 3D InCites · www.3dincites.com · 17,168 chars · fetch status success
Source sanity (S1) ok — passed before any model call (no s1_ block recorded)
Model / prompt MiniMax-M3 · prompt Blog Agent - News Summary (v2.8-final) · 9,726 tokens · 20.9s · run completed
Gate verdict hold · 5/6 applicable checks passed · spec v2.9 · C10 ratio 0.007647 · C10 rounds 0

上述每一行均由流水线生成，而非人工撰写。

编辑评分

确定性校验结果——纯 PHP 实现，判定过程不涉及模型
校验评分明细 6 项适用检查， 5项通过： 83 %. Hold items: C13 (falsifiable forecast) — sent to human review. Gate spec: v2.9 (S0 + S1 + C1–C20) · Source affinity (C20): 0.7389. 适用检查已通过 5 / 6 = 83% · 判定： hold Hold items: C13 (falsifiable forecast) — sent to human review Gate spec: v2.9 (S0 + S1 + C1–C20) · Source affinity (C20): 0.7389 是否发布由校验决定。独立审计评分仅供参考。

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来源

  1. Can Embedded Passives Fix AI's Power Delivery Problem? — https://www.3dincites.com/2026/10/can-embedded-passives-fix-ais-power-delivery-problem/ · rss · 访问于

事实标注为 S1/S2，并可追溯至所链接的来源。标注为 分析 的内容是 XAIPART 自身的推理，与报道的事实分开呈现。来源链接会被访问核实，而非 nofollow ——署名是有意为之。