Reported by 3D InCites on 2026-10-06. Summarized and analyzed by XAIPART Editorial.
What happened
Power electronics vendors are racing to deliver voltage regulators that can handle the multi-kilowatt currents required by AI GPUs and HPC accelerators, but the surrounding discrete inductors and capacitors are starting to dominate board real estate and limit performance.S1
The article describes power delivery as a stack of conversion losses from the rack to the die. Most data center racks use a 54-V/48-V backplane; accelerator boards then drop to 12 V through a 48-to-12-V VRM, followed by lateral 12-V-to-POL VRMs around the chip. As chips move to advanced process nodes, core voltages fall to 0.6-0.8 V while thermal design power (TDP) climbs to multiple kilowatts, so the PDN current P/V rises sharply and resistive (I²R) losses grow exponentially with it.S1
Saras Micro Devices' STILE technology integrates capacitors (and, in future generations, inductors) into the IC package substrate or PCB rather than mounting them on the surface. The capacitors are made to match the substrate thickness, use 3D pass-through copper terminations, show almost no capacitance derating under temperature and bias, and are rated for operation at 125°C.S1 Today's STILE parts target output capacitance for VRMs serving extreme transient loads; a higher-frequency generation with both decoupling capacitance and inductance is under development.S1
The article frames STILE as an enabler for vertical power delivery (VPD). Because the underside of today's boards is crowded with surface-mount decoupling capacitors, those parts block the move of VRMs directly under the chip. Embedding passives inside the substrate or PCB frees the underside for VPD and shortens the regulator-to-load path, reducing parasitic resistance and inductance.S1 Shaun Bowers, SVP of Product Management at Saras Micro Devices, expects the PDN to evolve first toward VPD, then toward higher rack and intermediate voltages, and eventually toward integrated voltage regulators (IVRs) inside the package or on the die, with VPD remaining the front-end stage for those IVRs.S1
| Metric | Reported value | Source |
|---|---|---|
| Rack backplane voltage | 54 V / 48 V | [S1] |
| Board-level intermediate rail | 12 V | [S1] |
| Processor core operating voltage | 0.6 to 0.8 V | [S1] |
| Thermal design power range cited | Multiple kilowatts per device | [S1] |
| Data center power scale cited | Approaching gigawatt level | [S1] |
| STILE capacitor operating temperature rating | 125°C | [S1] |
| Capacitance derating vs temperature/bias | Reported as almost none | [S1] |
| Higher-frequency STILE generation | Not disclosed (under development) | [S1] |
Background timeline
- No prior milestones disclosed by the source.
XAIPART take
Technical impact
Embedding output-stage capacitance directly under the die cuts the loop inductance and resistance between the last VRM stage and the silicon, which is exactly the regime where AI accelerator transients cause the largest voltage excursions. XAIPART analysis Pairing STILE-class parts with a 48-V-to-POL topology lets designers push the first high-frequency conversion step closer to the load, but thermal co-design becomes the gating issue: every part in the PDN now sits inside the package's hot-spot envelope, and CTE mismatch between copper, substrate laminate and the silicon die can dominate warpage at reflow.
Market impact
The bottleneck narrative in this brief is consistent with what hyperscalers have been signaling on 48-V rack architectures and VPD, but the article is one vendor's viewpoint and one interview. XAIPART analysis If substrate-embedded passives reach volume, the displaced surface-mount MLCC and power-inductor lines serving accelerator boards face a structural demand shift, while substrate and PCB manufacturers gain a higher-value embedding step. Sourcing teams should expect STILE-grade parts to remain single-source for at least the next design cycle.
Action
For procurement, request samples and a roadmap from Saras Micro Devices for STILE output-capacitance parts and the higher-frequency capacitor-plus-inductor generation before locking the PDN bill of materials. XAIPART analysis For design, evaluate VPD feasibility jointly with the embedded-passive supplier so the PCB underside is reserved for VRM landing, and add a 125°C derating check, reflow-profile warpage budget and CTE map to the package-level PDN review.
XAIPART Forecast
If a major hyperscaler or accelerator OEM publicly references Saras Micro Devices STILE in a shipping reference design by 2027-09-30, XAIPART expects at least two competing embedded-passive suppliers (existing MLCC or advanced-substrate vendors) to announce competing package-substrate-embedded PDN products within 9 months of that disclosure; otherwise this forecast is wrong. XAIPART analysis
Facts are as reported by the cited source. The design-in, sourcing and forward-looking statements above are XAIPART's analysis, not the source's claims. Uncertainty: this brief rests on a single interview-based article from one vendor (Saras Micro Devices) and one executive; product roadmap, volume, pricing and customer adoption are not disclosed.
Corrections: none at publication. This brief will be updated with a timestamp if the source corrects its report.
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|---|---|---|---|
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주시할 사항
| 주장 | 임계값 | 작성: | 상태 |
|---|---|---|---|
| If a major hyperscaler or accelerator OEM publicly references Saras Micro Devices STILE in a shipping reference design by 2027-09-30, XAIPART expects at least two competing embedded-passive suppliers (existing MLCC or... | a major hyperscaler or accelerator OEM publicly references Saras Micro Devices STILE in a shipping reference design by 2027-09-30, XAIPART expects at least two competing embedded-passive suppliers (existing MLCC or advanced-substrate ven... | Pending |
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| Dimension | FRED series ID | Unit | Lag | As of |
|---|---|---|---|---|
| Input cost | PCOPPUSDM, PALUMUSDM, PNICKUSDM | USD/mt | 96 d | |
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| FX & energy | DEXCHUS, DCOILBRENTEU, DHHNGSP | rate / USD/bbl / USD/MMBtu | 6 d |
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이 콘텐츠의 제작 방식
프로세스 증거 — 수집, 출처 온전성, 모델 및 게이트
| Source fetched | 3D InCites · www.3dincites.com · 17,168 chars · fetch status success |
|---|---|
| Source sanity (S1) | ok — passed before any model call (no s1_ block recorded) |
| Model / prompt | MiniMax-M3 · prompt Blog Agent - News Summary (v2.8-final) · 9,726 tokens · 20.9s · run completed |
| Gate | verdict hold · 5/6 applicable checks passed · spec v2.9 · C10 ratio 0.007647 · C10 rounds 0 |
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