5M240ZM68I5N vs EPM240ZM100C7N 对比
详细并排对比 5M240ZM68I5N 出自 Intel 和 EPM240ZM100C7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | 5M240ZM68I5N | EPM240ZM100C7N |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $1.25 | $6.10 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Series | MAX V | MAX II |
| Logic Elements | 240 | 240 |
| Number of Macrocells | 192 | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Configuration Memory | Nonvolatile Flash | On-chip non-volatile flash |
| Package Type | TFBGA-68 | — |
| Number of Terminals | 68 (ball) | — |
| Package Code | TFBGA | — |
| Form of Terminal | Ball | — |
| Package Shape | Square | — |
| Operating Temperature Grade | Industrial | — |
| JTAG Interface | TMS, TDI, TDO, TCK (Bank 1) | — |
| Programming Method | JTAG / in-system programmable | — |
| 电源电压 | [DATA_NEEDED: VCCINT and VCCIO levels] | — |
| I/O Standards | Multiple (LVTTL, LVCMOS, SSTL, etc., per MAX V doc; PCI and 1.2 V LVCMOS excluded for JTAG pins) | — |
| 安装类型 | Surface Mount | Surface Mount (BGA) |
| RoHS 状态 | Compliant | — |
| Lead Free | Yes | — |
| Family | — | MAX II Z |
| Macrocells | — | 192 |
| Pin-to-Pin Logic Delay (tPD) | — | 7.5 ns |
| User I/Os | — | 80 |
| User Flash Memory (UFM) | — | 8 Kbits |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| 封装 | — | 100-MBGA (Micro FineLine BGA), 6 x 6 mm |
| Process Technology | — | 0.18 µm 6-layer-metal flash |
| JTAG Support | — | IEEE 1149.1 (programming + boundary-scan) |
| 工作温度 | — | 0 °C to +85 °C (commercial) |
| Lead-Free / RoHS | — | Compliant per datasheet |