CDK2308CILP64 vs CDK2308DILP64 对比
详细并排对比 CDK2308CILP64 出自 MaxLinear 和 CDK2308DILP64 出自 MaxLinear。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | CDK2308CILP64 | CDK2308DILP64 |
|---|---|---|
| 品牌 | MaxLinear | MaxLinear |
| 分类 | ADC/DAC | ADC/DAC |
| 生命周期状态 | 有效 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.85 | $9.85 |
| 分辨率 | 10 bit | 10 bit |
| Number of Channels | 2 (dual) | 2 (Dual) |
| Sample Rate (max) | 65 MSPS per channel | — |
| Architecture | Pipelined | Pipelined ADC |
| Input Type | Differential, single-ended capable | Single-ended analog |
| Analog Supply Voltage | 3.3 V | — |
| Digital Output Supply | 1.8 V to 3.3 V | — |
| Digital Output Interface | Parallel CMOS | — |
| Data Rate (per channel) | Up to 65 MSPS | — |
| Reference | Internal bandgap; external reference supported | — |
| Sample-Rate Family | 20 / 40 / 65 / 80 MSPS (per datasheet family) | — |
| 封装 | 64-pin QFN with Exposed Pad (EP) | 64-QFN (9x9 mm) |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度 | -40 C to +85 C (industrial) | — |
| RoHS 状态 | Compliant | Compliant |
| Sampling Rate (max) | — | 80 MSPS |
| Supported Sample Rates | — | 20 / 40 / 65 / 80 MSPS (programmable) |
| Power Dissipation | — | 78 mW per channel at 80 MSPS |
| Supply Voltage (AVDD) | — | [DATA_NEEDED: AVDD nominal voltage] |
| Supply Voltage (DRVDD) | — | [DATA_NEEDED: DRVDD nominal voltage] |
| Input Bandwidth | — | [DATA_NEEDED: -3 dB input bandwidth] |
| SNR | — | [DATA_NEEDED: SNR at full scale] |
| SFDR | — | [DATA_NEEDED: SFDR] |
| ENOB | — | [DATA_NEEDED: effective number of bits] |
| 工作温度范围 | — | -40 C to +85 C |
| MSL 等级 | — | [DATA_NEEDED: MSL rating] |
| Power-Down Modes | — | Per-channel standby, chip standby, full power-down |
| Track-and-Hold Amplifier | — | Integrated, optimized for IF frequencies |