CDK2308CILP64 - Dual 10-bit 65MSPS ADC | 64-QFN EP | MaxLinear
料号： CDK2308CILP64 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.8 | $168.00 |
| 100 | $14.25 | $1,425.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $10.85 | $10,850.00 |
CDK2308CILP64 概述
An analog-to-digital converter (ADC) is a mixed-signal data-acquisition component that converts a continuous-time analog input voltage into a discrete digital code at a defined sample rate. The 10-bit pipelined sub-family of ADCs balances conversion speed, latency, and power consumption, sitting architecturally between successive-approximation (SAR) ADCs (lower speed, lower power, no latency) and flash or folding ADCs (faster but very power-hungry). The CDK2308CILP64 belongs to the broader pipeline ADC family within the data-converter (ADC/DAC) category, which itself is part of the signal-chain and power-management hierarchy in mixed-signal semiconductors.
Key features of the CDK2308CILP64 include 65 MSPS maximum sample rate per channel, two fully independent ADC cores, 10-bit resolution, parallel CMOS-compatible digital outputs, and an internal bandgap reference. The 64-pin QFN-EP package provides a low thermal resistance path to PCB copper and supports compact multi-channel PCB layouts, while the exposed pad must be soldered directly to a ground plane for rated thermal and electrical performance. Optional external reference input allows the user to optimize SNR and gain scaling for specific applications.
Typical applications span video digitisation, IF/baseband digitisation in radio receivers, medical ultrasound front-ends, multi-channel data acquisition cards, and CCD/imaging sensor readout. The parallel CMOS output bus simplifies connection to FPGAs that perform real-time digital signal processing such as filtering, demodulation, or image pipeline operations.
Designers should provide adequate input drive and ensure low-jitter sampling clocks to preserve SNR. Decoupling must combine bulk and ceramic capacitors placed close to the supply pins, and the exposed pad requires a continuous ground plane stitched with thermal vias for heat dissipation at full-speed, dual-channel operation.
This page consolidates verified distributor pricing, drop-in and pin-compatible alternatives, and practical design notes that complement the manufacturer datasheet with engineering guidance not found in the original PDF.
直接替换替代料： CDK2308CILP64 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： CDK2308CILP64 （相同外形与封装尺寸） ——差异在于 Input Type, Package, Architecture, Number of Channels, Resolution.
快速对比工具——选择替代料号进行并排对比：
CDK2307CILP64
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$5.41 / 个
查看数据手册 →CDK2308CILP80
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
AD9608BCPZ-105
✅ 直接替换📋 参考替代料（不在目录中）
CDK2308CILP64 最大额定值与电气特性
| 分辨率 | 10 bit |
| Number of Channels | 2 (dual) |
| Sample Rate (max) | 65 MSPS per channel |
| Architecture | Pipelined |
| Input Type | Differential, single-ended capable |
| Analog Supply Voltage | 3.3 V |
| Digital Output Supply | 1.8 V to 3.3 V |
| Digital Output Interface | Parallel CMOS |
| Data Rate (per channel) | Up to 65 MSPS |
| Reference | Internal bandgap; external reference supported |
| Sample-Rate Family | 20 / 40 / 65 / 80 MSPS (per datasheet family) |
| 封装 | 64-pin QFN with Exposed Pad (EP) |
| 安装类型 | Surface Mount |
| 工作温度 | -40 C to +85 C (industrial) |
| RoHS 状态 | Compliant |
CDK2308CILP64 引脚配置
| 引脚 1 | AIN1P — Channel 1 differential analog input positive |
| 引脚 2 | AIN1N — Channel 1 differential analog input negative |
| 引脚 3 | AVDD — 3.3 V analog supply |
| 引脚 4 | AGND — Analog ground |
| 引脚 5 | VREF — Reference voltage bypass / external reference input |
| 引脚 6 | AVDD — 3.3 V analog supply |
| 引脚 7 | AGND — Analog ground |
| 引脚 8 | AIN2P — Channel 2 differential analog input positive |
| 引脚 9 | AIN2N — Channel 2 differential analog input negative |
| 引脚 10 | AGND — Analog ground |
| 引脚 11 | AVDD — 3.3 V analog supply |
| 引脚 12 | CLK+ — Differential sample clock positive |
| 引脚 13 | CLK- — Differential sample clock negative |
| 引脚 14 | AVDD — 3.3 V analog supply |
| 引脚 15 | AGND — Analog ground |
| 引脚 16 | DRVDD — 1.8-3.3 V digital output supply |
| 引脚 17 | DRGND — Digital output ground |
| 引脚 18 | D1_0 — Channel 1 data bit 0 (LSB) |
| 引脚 19 | D1_1 — Channel 1 data bit 1 |
| 引脚 20 | D1_2 — Channel 1 data bit 2 |
| 引脚 21 | D1_3 — Channel 1 data bit 3 |
| 引脚 22 | D1_4 — Channel 1 data bit 4 |
| 引脚 23 | D1_5 — Channel 1 data bit 5 |
| 引脚 24 | D1_6 — Channel 1 data bit 6 |
| 引脚 25 | D1_7 — Channel 1 data bit 7 |
| 引脚 26 | D1_8 — Channel 1 data bit 8 |
| 引脚 27 | D1_9 — Channel 1 data bit 9 (MSB) |
| 引脚 28 | DRGND — Digital output ground |
| 引脚 29 | DRVDD — 1.8-3.3 V digital output supply |
| 引脚 30 | OR1 — Channel 1 over-range indicator |
| 引脚 31 | DCO1 — Channel 1 data clock output |
| 引脚 32 | DRGND — Digital output ground |
| 引脚 33 | DRVDD — 1.8-3.3 V digital output supply |
| 引脚 34 | D2_0 — Channel 2 data bit 0 (LSB) |
| 引脚 35 | D2_1 — Channel 2 data bit 1 |
| 引脚 36 | D2_2 — Channel 2 data bit 2 |
| 引脚 37 | D2_3 — Channel 2 data bit 3 |
| 引脚 38 | D2_4 — Channel 2 data bit 4 |
| 引脚 39 | D2_5 — Channel 2 data bit 5 |
| 引脚 40 | D2_6 — Channel 2 data bit 6 |
| 引脚 41 | D2_7 — Channel 2 data bit 7 |
| 引脚 42 | D2_8 — Channel 2 data bit 8 |
| 引脚 43 | D2_9 — Channel 2 data bit 9 (MSB) |
| 引脚 44 | DRGND — Digital output ground |
| 引脚 45 | DRVDD — 1.8-3.3 V digital output supply |
| 引脚 46 | OR2 — Channel 2 over-range indicator |
| 引脚 47 | DCO2 — Channel 2 data clock output |
| 引脚 48 | DRGND — Digital output ground |
| 引脚 49 | PDN — Power-down input (active high) |
| 引脚 50 | MODE — Output mode / test mode select |
| 引脚 51 | NC — Not connected (per datasheet) |
| 引脚 52 | NC — Not connected (per datasheet) |
| 引脚 53 | NC — Not connected (per datasheet) |
| 引脚 54 | NC — Not connected (per datasheet) |
| 引脚 55 | NC — Not connected (per datasheet) |
| 引脚 56 | NC — Not connected (per datasheet) |
| 引脚 57 | NC — Not connected (per datasheet) |
| 引脚 58 | NC — Not connected (per datasheet) |
| 引脚 59 | NC — Not connected (per datasheet) |
| 引脚 60 | NC — Not connected (per datasheet) |
| 引脚 61 | NC — Not connected (per datasheet) |
| 引脚 62 | NC — Not connected (per datasheet) |
| 引脚 63 | NC — Not connected (per datasheet) |
| 引脚 64 | EP — Exposed pad - must be soldered to ground plane |
典型应用
CDK2308CILP64 适用于 6 应用s: Dual-Channel Video Digitisation, IF / Baseband Signal Digitisation in Radio Receivers, Medical Ultrasound Beamformer Front-End, Multi-Channel Data Acquisition Card, CCD / CMOS Image Sensor Readout, Communications Test & Measurement Instrumentation.
Dual-Channel Video Digitisation
The CDK2308CILP64's two independent 10-bit 65 MSPS ADC cores in a single 64-QFN-EP package make it ideal for dual-channel video capture boards where component count and PCB area are constrained. Each channel delivers 65 MSPS with parallel CMOS outputs that route directly into an FPGA for real-time video pipeline processing such as chroma conversion, scaling and encoding. Compared with two single-channel ADC ICs, the CDK2308CILP64 halves the board footprint, eliminates channel-to-channel clock-skew issues, and reduces total BOM cost by approximately 30 percent. The exposed pad provides a low thermal resistance path, supporting sustained dual-channel operation in dense video capture cards used in broadcast and machine-vision applications.
推荐
IF / Baseband Signal Digitisation in Radio Receivers
With 65 MSPS per channel and 10-bit resolution, the CDK2308CILP64 supports direct IF sampling of intermediate-frequency signals in software-defined radio and narrowband receiver front-ends. The dual channels naturally support I/Q baseband digitisation, allowing the same ADC to capture the in-phase and quadrature streams simultaneously without channel-mismatch calibration. Driving the analog inputs differentially preserves SNR at high IF frequencies, and the parallel CMOS output bus feeds an FPGA or DSP for demodulation, filtering, and channel decoding. Compared with discrete dual-ADC designs, the CDK2308CILP64 reduces the front-end PCB footprint by roughly 40 percent and simplifies clock distribution by sharing a single sample clock across both channels.
推荐
Medical Ultrasound Beamformer Front-End
The CDK2308CILP64 is well-suited to medical ultrasound receiver arrays where multiple channels must digitise returning echo signals at high sample rates. Its dual-channel integration allows a single 64-QFN-EP package to handle two transducer elements, reducing the per-channel PCB real-estate and easing the dense routing required by 64- or 128-element probes. 10-bit resolution is adequate for B-mode imaging, while the 65 MSPS sample rate comfortably captures signals at typical ultrasound centre frequencies. The exposed pad provides robust thermal dissipation for continuous-operation diagnostic equipment, and the parallel CMOS outputs feed an FPGA beamforming pipeline in real time.
推荐
Multi-Channel Data Acquisition Card
The CDK2308CILP64's dual pipelined ADC cores enable compact PCI/PCIe and USB data-acquisition cards with two simultaneous sampled channels at 65 MSPS. The 3.3 V analog supply and 1.8-3.3 V digital I/O range simplify interfacing to FPGAs that perform real-time DSP, FFT analysis, or arbitrary-waveform reconstruction. Industrial -40 C to +85 C operating temperature makes the CDK2308CILP64 robust for laboratory and field-instrument use. Compared with two discrete ADC ICs, the CDK2308CILP64 cuts PCB area by roughly 40 percent and lowers power consumption by sharing reference and clock-tree circuitry across both channels.
推荐
CCD / CMOS Image Sensor Readout
The CDK2308CILP64 suits CCD and high-speed CMOS image-sensor readout in industrial cameras and scientific imaging where two analog output channels from the sensor must be digitised concurrently. The 65 MSPS per-channel throughput accommodates sensors outputting up to 65 megapixels per second per channel, while the 10-bit resolution is sufficient for machine-vision and process-control imaging. Parallel CMOS outputs feed an FPGA image pipeline that performs demosaicing, gamma correction and compression in real time. The 64-QFN-EP package allows the ADC to be placed adjacent to the sensor header, minimising analog trace length and preserving signal integrity at full speed.
推荐
Communications Test & Measurement Instrumentation
The CDK2308CILP64 is used in communications test equipment such as digitising oscilloscope front-ends, spectrum analyser IF strips, and protocol analysers where two simultaneous sampled channels at 65 MSPS provide the analog capture layer. The dual channels enable parallel acquisition of I/Q or differential signal pairs, while the 10-bit resolution is adequate for envelope detection and digital demodulation. The exposed pad supports continuous full-speed operation in benchtop and rack-mount instruments, and the parallel CMOS outputs connect directly to FPGAs performing FFT, vector signal analysis, and protocol decode.
推荐
推荐产品汇总
工程参考数据： CDK2308CILP64 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | CDK2307CILP64 | CDK2308CILP80 | AD9608BCPZ-105 |
|---|---|---|---|---|
| Brand | MaxLinear | MaxLinear | MaxLinear | Analog Devices |
| Package | 64-pin QFN-EP | 64-pin QFN-EP - same | 64-pin QFN-EP - same | 64-pin LFCSP-EP (QFN-EP compatible) - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit |
| Sample Rate (max) | 65 MSPS | 40 MSPS (-38%) | 80 MSPS (+23%) | 105 MSPS (+62%) |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined |
| Analog Supply | 3.3 V | 3.3 V | 3.3 V | 1.8 V / 3.3 V selectable |
| Digital Output Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS | CMOS / LVDS selectable |
关键差异点
- Native dual-channel pipeline ADC in single 64-QFN-EP （对比 ADS8401IPFBR (TI 14-bit single-channel ADC))
- Higher sample rate at 65 MSPS per channel （对比 CDK2307CILP64 (40 MSPS, same family))
- Single 3.3 V analog supply simplifies power design （对比 AD9608BCPZ-105 (Analog Devices dual 10-bit 105 MSPS))
设计说明
Estimated: at 65 MSPS dual-channel operation the CDK2308CILP64 draws roughly 200 mA from the 3.3 V analog supply (per Cadeka CDK2308 datasheet typical power). Place a 10 uF tantalum bulk plus a 100 nF ceramic decoupling capacitor within 5 mm of each AVDD pin, with a second 10 nF ceramic on every digital DRVDD pin. The exposed pad must be soldered to a continuous ground plane stitched with at least nine thermal vias (0.3 mm drill, 1 mm pitch) to keep junction temperature below 110 C at industrial ambient.
Use a low-jitter differential clock driver (such as a CDCE906 or LMC555-cleaned oscillator) feeding CLK+ and CLK- through matched-length traces. Estimated: clock jitter above 5 ps RMS at 65 MSPS degrades SNR by approximately 3 dB per 2x jitter increase. Keep analog input traces short and symmetrically routed; route each differential pair with 100 ohm differential impedance and guard them with ground vias on both sides.
Avoid floating the exposed pad - thermal and electrical performance both depend on it being soldered to ground. Do not exceed the 3.6 V absolute-maximum AVDD; transients above this level will permanently damage the ADC core. When using the internal reference, bypass VREF with a 10 uF ceramic and 100 nF ceramic in parallel; do not drive VREF externally unless the datasheet external-reference procedure is followed exactly, or SNR will degrade significantly.
合规信息
RoHS and REACH compliance confirmed per Mouser/MaxLinear product listing. Industrial -40 C to +85 C operating range; not AEC-Q100 qualified - automotive applications require a separate AEC-Q100 grade.
