EP1810JC-25 vs EP1810GC-35 对比
详细并排对比 EP1810JC-25 出自 Intel 和 EP1810GC-35 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1810JC-25 | EP1810GC-35 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $6.80 | $177.12 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera/Intel Classic EPLD (EP1810 series) | — |
| Macrocells | 48 | 16 |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | — |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| 工作温度 | -40 °C to 85 °C (industrial, per distributor listings) | [DATA_NEEDED: operating temperature range] |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | CMOS, UV-erasable EPROM cells |
| 封装 | 28-pin ceramic DIP (J) with quartz window | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| 安装类型 | Through-hole | Through Hole |
| Erasure Method | UV light (windowed package) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | Not applicable (legacy ceramic package) |
| 生命周期状态 | NRND (Not Recommended for New Designs) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Family | — | Altera Classic EPLD |
| 引脚数 | — | 68 |
| Propagation Delay (tpd max) | — | 40 ns |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| I/O Standard | — | TTL-compatible |
| Programming Method | — | UV erasure + EPROM programming |
| 电源电压 | — | [DATA_NEEDED: VCC range] |
| Lead-Free Status | — | Not applicable |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |