EP1810JC-25 vs EP1810GC-35 비교
다음의 상세 나란히 비교: EP1810JC-25 제조: Intel 및 EP1810GC-35 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1810JC-25 | EP1810GC-35 |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | 최종 구매 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $6.80 | $177.12 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera/Intel Classic EPLD (EP1810 series) | — |
| Macrocells | 48 | 16 |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | — |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| 동작 온도 | -40 °C to 85 °C (industrial, per distributor listings) | [DATA_NEEDED: operating temperature range] |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | CMOS, UV-erasable EPROM cells |
| 패키지 | 28-pin ceramic DIP (J) with quartz window | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| 실장 유형 | Through-hole | Through Hole |
| Erasure Method | UV light (windowed package) | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance status] | Not applicable (legacy ceramic package) |
| 수명 주기 상태 | NRND (Not Recommended for New Designs) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Family | — | Altera Classic EPLD |
| 핀 수 | — | 68 |
| Propagation Delay (tpd max) | — | 40 ns |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| I/O Standard | — | TTL-compatible |
| Programming Method | — | UV erasure + EPROM programming |
| 공급 전압 | — | [DATA_NEEDED: VCC range] |
| Lead-Free Status | — | Not applicable |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |