EP1810JC-25 vs EP1810GC-35 比較
詳細な並列比較: EP1810JC-25 メーカー: Intel および EP1810GC-35 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1810JC-25 | EP1810GC-35 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $6.80 | $177.12 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera/Intel Classic EPLD (EP1810 series) | — |
| Macrocells | 48 | 16 |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | — |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| 動作温度 | -40 °C to 85 °C (industrial, per distributor listings) | [DATA_NEEDED: operating temperature range] |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | CMOS, UV-erasable EPROM cells |
| パッケージ | 28-pin ceramic DIP (J) with quartz window | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| 実装タイプ | Through-hole | Through Hole |
| Erasure Method | UV light (windowed package) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | Not applicable (legacy ceramic package) |
| ライフサイクル状態 | NRND (Not Recommended for New Designs) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Family | — | Altera Classic EPLD |
| ピン数 | — | 68 |
| Propagation Delay (tpd max) | — | 40 ns |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| I/O Standard | — | TTL-compatible |
| Programming Method | — | UV erasure + EPROM programming |
| 電源電圧 | — | [DATA_NEEDED: VCC range] |
| Lead-Free Status | — | Not applicable |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |