EP1810JC-35 vs EP1810GC-35 对比
详细并排对比 EP1810JC-35 出自 Intel 和 EP1810GC-35 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1810JC-35 | EP1810GC-35 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $5.48 | $177.12 |
| Device Family | Classic EPLD (EP1810) | — |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | EPLD (Erasable Programmable Logic Device) |
| Number of Macrocells | 48 | — |
| Propagation Delay (tpd) | 35 ns (max) | — |
| 最大时钟频率 | [DATA_NEEDED: fmax for this speed grade] | — |
| Process Technology | CMOS | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | — |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | — |
| Number of Terminals | 68 | — |
| Terminal Form | J-Bend | — |
| 工作温度范围 | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | — |
| Erasure Method | UV (quartz-windowed ceramic package) | — |
| RoHS 状态 | Compliant (per Altera listing) | Not applicable (legacy ceramic package) |
| Lead-Free Status | Lead-free (per distributor listing) | Not applicable |
| 安装类型 | Surface Mount (J-Lead) | Through Hole |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Logic Family | — | Altera Classic EPLD |
| Technology | — | CMOS, UV-erasable EPROM cells |
| 封装 | — | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| 引脚数 | — | 68 |
| Propagation Delay (tpd max) | — | 40 ns |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Macrocells | — | 16 |
| I/O Standard | — | TTL-compatible |
| Programming Method | — | UV erasure + EPROM programming |
| 工作温度 | — | [DATA_NEEDED: operating temperature range] |
| 电源电压 | — | [DATA_NEEDED: VCC range] |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |