EP1810JC-35 vs EP1810GC-35 비교
다음의 상세 나란히 비교: EP1810JC-35 제조: Intel 및 EP1810GC-35 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1810JC-35 | EP1810GC-35 |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | 최종 구매 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $5.48 | $177.12 |
| Device Family | Classic EPLD (EP1810) | — |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | EPLD (Erasable Programmable Logic Device) |
| Number of Macrocells | 48 | — |
| Propagation Delay (tpd) | 35 ns (max) | — |
| 최대 클록 주파수 | [DATA_NEEDED: fmax for this speed grade] | — |
| Process Technology | CMOS | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | — |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | — |
| Number of Terminals | 68 | — |
| Terminal Form | J-Bend | — |
| 동작 온도 범위 | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | — |
| Erasure Method | UV (quartz-windowed ceramic package) | — |
| RoHS 상태 | Compliant (per Altera listing) | Not applicable (legacy ceramic package) |
| Lead-Free Status | Lead-free (per distributor listing) | Not applicable |
| 실장 유형 | Surface Mount (J-Lead) | Through Hole |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Logic Family | — | Altera Classic EPLD |
| Technology | — | CMOS, UV-erasable EPROM cells |
| 패키지 | — | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| 핀 수 | — | 68 |
| Propagation Delay (tpd max) | — | 40 ns |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Macrocells | — | 16 |
| I/O Standard | — | TTL-compatible |
| Programming Method | — | UV erasure + EPROM programming |
| 동작 온도 | — | [DATA_NEEDED: operating temperature range] |
| 공급 전압 | — | [DATA_NEEDED: VCC range] |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |