EP1810JC-35 vs EP1810LC-35 对比

详细并排对比 EP1810JC-35 出自 Intel 和 EP1810LC-35 出自 Rochester Electronics。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Rochester Electronics
EP1810LC-35 EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera

EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera

EP1810LC-35 ⚠ 最后一次采购

规格对比

参数 EP1810JC-35 EP1810LC-35
品牌 Intel Rochester Electronics
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $5.48 $49.20
Device Family Classic EPLD (EP1810) —
Device Type UV-Erasable Complex PLD (UV PLD / CPLD) EPLD (Erasable Programmable Logic Device)
Number of Macrocells 48 —
Propagation Delay (tpd) 35 ns (max) 35 ns (max, '-35' speed grade)
最大时钟频率 [DATA_NEEDED: fmax for this speed grade] —
Process Technology CMOS —
Supply Voltage (Vcc) 5 V (nominal) —
Maximum Supply Voltage 5.25 V (per distributor listing) —
Package Type CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) —
Number of Terminals 68 —
Terminal Form J-Bend —
工作温度范围 0°C to 70°C (Commercial) —
Temperature Grade Commercial —
Erasure Method UV (quartz-windowed ceramic package) —
RoHS 状态 Compliant (per Altera listing) [DATA_NEEDED]
Lead-Free Status Lead-free (per distributor listing) —
安装类型 Surface Mount (J-Lead) Surface Mount (socketable)
Logic Architecture Programmable AND/OR array with macrocell outputs —
Series — Classic EP1810
Macrocells — 48
Equivalent Gates — 900 usable / 2100 equivalent
Maximum Operating Frequency — 28.6 MHz
Supply Voltage (VCC) — 5 V (4.75 V to 5.25 V)
Technology — CMOS, UV-erasable EPROM
封装 — 68-pin PLCC (J-Lead)
工作温度 — 0C to +70C (commercial)
I/O Pins — [DATA_NEEDED: I/O count exact]
Configuration Method — UV-erase + EPROM programmer
Programmable Interconnect — Centralized Programmable Interconnect Array (PIA)
Development Tool (legacy) — MAX+PLUS II / A+PLUS
Lead-Free — [DATA_NEEDED]

数据手册与资源

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