EP1810JC-45 vs EP1810GC-35 对比
详细并排对比 EP1810JC-45 出自 Altera 和 EP1810GC-35 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1810JC-45 | EP1810GC-35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $21.10 | $177.12 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP1810 (Classic EPLD Family) | — |
| Macrocells | 48 | 16 |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | — |
| 最大时钟频率 | 33.3 MHz | — |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable EPROM cells |
| Maximum Supply Voltage | 5.25 V | — |
| 封装 | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| 引脚数量 | 68 | — |
| Package Code | QCCJ | — |
| Temperature Grade | Commercial | — |
| 安装类型 | Surface Mount | Through Hole |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance not stated in verified data] | Not applicable (legacy ceramic package) |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Family | — | Altera Classic EPLD |
| 引脚数 | — | 68 |
| Propagation Delay (tpd max) | — | 40 ns |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| I/O Standard | — | TTL-compatible |
| Programming Method | — | UV erasure + EPROM programming |
| 工作温度 | — | [DATA_NEEDED: operating temperature range] |
| 电源电压 | — | [DATA_NEEDED: VCC range] |
| Lead-Free Status | — | Not applicable |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |