EP1810JC35 vs EP1810JC-25 비교
다음의 상세 나란히 비교: EP1810JC35 제조: Altera 및 EP1810JC-25 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1810JC35 | EP1810JC-25 |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.75 | $6.80 |
| Family | Altera Classic EPLD | Altera/Intel Classic EPLD (EP1810 series) |
| Product Type | UV-erasable / OTP Complex PLD (EPLD) | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | 48 | 48 |
| Logic Gates (typ.) | [DATA_NEEDED: logic gates count] | — |
| Maximum User I/O Pins | [DATA_NEEDED: user I/O count for PLCC-68] | — |
| Propagation Delay (tPD) | 35 ns | 25 ns |
| 최대 클록 주파수 | 40 MHz | — |
| Supply Voltage (VCC max) | 5.25 V | — |
| Supply Voltage (VCC min) | [DATA_NEEDED: VCC minimum] | — |
| Process Technology | CMOS EPROM cell | — |
| 동작 온도 | 0 C to +70 C (Commercial) | -40 °C to 85 °C (industrial, per distributor listings) |
| 패키지 | PLCC-68 (J-lead, ceramic) | 28-pin ceramic DIP (J) with quartz window |
| Package Code | QCCJ | — |
| Terminal Form | J-BEND | — |
| Number of Terminals | 68 | — |
| Programming | UV-erase (windowed) or OTP | — |
| Development Tool | Altera MAX+plus II / A+plus | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance for EP1810JC35] | [DATA_NEEDED: RoHS compliance status] |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fMAX] |
| Input Lines | — | 60 (including I/O) |
| I/O Lines | — | 48 |
| Dedicated Inputs | — | 12 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Technology | — | CMOS, UV-erasable (windowed ceramic DIP) |
| 실장 유형 | — | Through-hole |
| Erasure Method | — | UV light (windowed package) |
| 수명 주기 상태 | — | NRND (Not Recommended for New Designs) |