EP1K50QC208-3 vs EP1K100QC208-3 对比

详细并排对比 EP1K50QC208-3 出自 Altera 和 EP1K100QC208-3 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1K50QC208-3 EP1K100QC208-3
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $12.10 $60.04
Family ACEX 1K —
Logic Elements / Cells 2,880 —
Typical Gates 50,000 —
RAM Bits 40,960 —
Logic Array Blocks (LABs) 360 624
Embedded Array Blocks (EABs) 12 —
User I/O Pins 147 —
Maximum Operating Frequency 166.67 MHz —
Speed Grade -3 -3
Core Supply Voltage 2.5 V 2.5 V
Process Technology 0.22 µm CMOS 0.22 um CMOS
封装 208-pin PQFP (BFQFP) —
安装类型 Surface Mount Surface Mount
工作温度 Commercial (0°C to +70°C) [DATA_NEEDED: exact range] —
Configuration Mode Passive Serial, Active Serial, JTAG —
I/O Standards LVTTL, LVCMOS, PCI —
Design Tool Support Quartus II, MAX+PLUS II —
RoHS 状态 unknown —
Product Family — ACEX 1K
Device Type — FPGA (Field Programmable Gate Array)
Typical Gate Count — 100,000 gates
Number of Logic Elements — 4,992
Total RAM Bits — 49,152 bits
Maximum User I/O — 147
Maximum Internal Clock Frequency — 200 MHz
Package Type — 208-Pin BFQFP (PQFP)
Number of Terminals — 208
Terminal Form — Gull Wing
Package Shape — Square
Temperature Grade — Commercial
RoHS / Lead-Free Suffix — No -N suffix; compliance not verified in retrieved source data
I/O Standards Supported — [DATA_NEEDED: supported I/O standards]
Configuration Memory — SRAM-based loadable PLD

数据手册与资源

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