EP1M350F780C5ES vs EP1M350F780C8 对比

详细并排对比 EP1M350F780C5ES 出自 Altera 和 EP1M350F780C8 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1M350F780C5ES EP1M350F780C8
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $142.00 $175.00
Family Mercury (EP1M) —
Logic Elements / Cells 14,400 —
Equivalent System Gates 350,000 —
Core Voltage (VCCINT) 1.71 V to 1.89 V (1.8 V nominal) —
Transceivers Integrated high-speed SERDES with CDR —
Transceiver Data Rate Up to 1.25 Gbps per channel —
I/O Voltage Banks Multiple, supporting mixed-voltage interfaces —
封装 780-pin FC-FBGA (Flip-Chip BGA) 780-ball FineLine BGA
Package Dimensions 29 mm x 29 mm —
安装类型 Surface Mount (BGA) Surface Mount (BGA)
工作温度 0C to +85C (commercial) 0C to +85C (commercial)
Architecture LUT-based with embedded CDR transceivers —
Compliance RoHS (per distributor listing; status: unknown) —
Lead-Free yes —
MSL 等级 [DATA_NEEDED: MSL rating] [DATA_NEEDED: MSL rating]
Device Family — Altera APEX Mercury (EP1M)
Typical Gates — 350,000
Maximum Logic Elements (LEs) — 12,160
Embedded RAM Blocks — 4 dual-port RAM blocks
Speed Grade — C8 (commercial, speed bin 8)
Supply Voltage (Core) — [DATA_NEEDED: core Vcc]
I/O Standards Supported — LVTTL, LVCMOS, PCI, SSTL, LVDS (up to 20 standards)
Global Clock Networks — 8
Configuration Interface — IEEE 1532 / passive serial / JTAG
Maximum User I/O — [DATA_NEEDED: user I/O count]
In-System Programmability — Yes (ISP via JTAG)
RoHS 状态 — unknown (legacy device)

数据手册与资源

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