EP1S20F672C6 vs EP1S20F672C7 对比
详细并排对比 EP1S20F672C6 出自 Altera 和 EP1S20F672C7 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1S20F672C6 | EP1S20F672C7 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $470.00 | $195.00 |
| Manufacturer | Altera (now Intel) | — |
| Series | Stratix | Stratix |
| Family | Stratix (first generation) | Altera Stratix FPGA |
| Process Technology | 0.13 µm CMOS | — |
| Logic Elements (LEs) | 18,460 | 18,460 |
| Logic Array Blocks (LABs) | 1,846 | — |
| Embedded Memory Bits | 1,669,248 | 1,669,248 |
| Maximum User I/Os | 426 | — |
| 封装 | 672-ball FineLine BGA | 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch) |
| Package Code | F672 | — |
| Speed Grade | C6 | C7 |
| 工作温度 | 0°C to +85°C (Commercial) | 0C to 85C (commercial) |
| 电源电压 | Core 1.5 V, I/O programmable | — |
| 安装类型 | Surface Mount | Surface Mount |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | unknown |
| User I/O Pins | — | 426 |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Logic Family | — | CMOS, SRAM-based |
| Core Supply Voltage | — | 1.5 V |
| Configuration Modes | — | JTAG, Passive Serial, Fast Passive Parallel, Active Serial |
| MSL 等级 | — | [DATA_NEEDED: MSL level] |
| Clock PLLs | — | Up to 10 |