EP1S20F672C6 - Stratix 18460 LEs FPGA 672-BBGA | Altera/Intel
料号： EP1S20F672C6 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $659.7 | $659.70 |
| 10 | $615 | $6,150.00 |
| 100 | $560 | $56,000.00 |
| 500 | $510 | $255,000.00 |
| 1,000 | $470 | $470,000.00 |
EP1S20F672C6 概述
A Field Programmable Gate Array (FPGA) is a reprogrammable semiconductor device containing an array of configurable logic blocks (CLBs), embedded memory, DSP blocks, and routing channels. Within the broader semiconductor hierarchy, an FPGA sits between fixed-function Application-Specific Integrated Circuits (ASICs) and software-programmable microcontrollers: it offers ASIC-class parallelism and throughput while retaining the flexibility of in-system reprogrammability. The Stratix family belongs to Altera's high-end programmable logic device family and pioneered embedded TriMatrix memory, DSP blocks, and dedicated high-speed serial interfaces in mainstream FPGAs.
Key features include 18,460 logic elements distributed across 1,846 Logic Array Blocks (LABs), 1,669,248 bits of embedded RAM organized in TriMatrix memory structures, embedded DSP blocks for high-throughput multiply-accumulate operations, and dedicated high-speed transceiver channels for gigabit serial I/O. The device supports multiple I/O standards including LVDS, LVTTL, LVCMOS, SSTL, and HSTL through programmable I/O elements. The 672-ball FineLine BGA package offers controlled-impedance signal routing and high pin-count density suitable for complex digital designs requiring extensive I/O connectivity.
The Stratix architecture incorporates dedicated hard IP blocks - including DSP blocks optimized for IEEE 754 single-precision floating-point operations, memory interface controllers, and high-speed serial transceivers - reducing the soft-logic footprint required for typical DSP and memory-intensive designs. The TriMatrix memory subsystem provides three distinct memory block sizes (M512, M4K, M-RAM) optimized for different application data widths and depths, enabling efficient implementation of FIFOs, look-up tables, and buffering functions. Quartus II design software is used for synthesis, place-and-route, and bitstream generation.
Typical applications include high-speed data acquisition systems, telecommunications line cards, software-defined radio base stations, video processing pipelines, and ASIC prototyping platforms. The combination of high logic density, embedded memory, DSP capability, and high-speed serial I/O makes the EP1S20F672C6 well suited for parallel processing tasks where microcontrollers and DSPs would be performance-limited.
When designing with this FPGA, designers must allocate sufficient PCB power-decoupling capacitance near each power pin, implement proper signal-integrity practices for high-speed LVDS pairs, and provide adequate thermal dissipation through PCB copper pours or forced airflow. Quartus II tool support requires legacy software versions since the Stratix family predates Intel's current Quartus Prime releases.
This page synthesizes distributor pricing, drop-in same-family alternatives with the same 672-BGA footprint, and practical design notes not consolidated in any single manufacturer document.
直接替换替代料： EP1S20F672C6 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EP1S20F672C6 （相同外形与封装尺寸） ——差异在于 Package, Operating Temperature, Speed Grade, Family, Logic Elements.
快速对比工具——选择替代料号进行并排对比：
EP1S20F672C7
✅ 直接替换✓ 有现货
$195 / 个
查看数据手册 →EP1S20F672C7N
✅ 直接替换✓ 有现货
$109.2 / 个
查看数据手册 →EP1S20F672C6N
✅ 直接替换✓ 有现货
$68.9 / 个
查看数据手册 →EP1S20F672I6N
✅ 直接替换📋 参考替代料（不在目录中）
EP1S20F672I6
✅ 直接替换📋 参考替代料（不在目录中）
EP1S25F672C6
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$125 / 个
查看数据手册 →EP1S20F672C6 最大额定值与电气特性
| Manufacturer | Altera (now Intel) |
| Series | Stratix |
| Family | Stratix (first generation) |
| Process Technology | 0.13 µm CMOS |
| Logic Elements (LEs) | 18,460 |
| Logic Array Blocks (LABs) | 1,846 |
| Embedded Memory Bits | 1,669,248 |
| Maximum User I/Os | 426 |
| 封装 | 672-ball FineLine BGA |
| Package Code | F672 |
| Speed Grade | C6 |
| 工作温度 | 0°C to +85°C (Commercial) |
| 电源电压 | Core 1.5 V, I/O programmable |
| 安装类型 | Surface Mount |
EP1S20F672C6 引脚配置
| 引脚 A1 | IO — User I/O (specific function depends on Quartus pin assignment) |
| 引脚 A2 | IO — User I/O |
| 引脚 A3 | VCCIO — I/O supply voltage |
| 引脚 A4 | GND — Ground |
| 引脚 B1 | IO — User I/O |
| 引脚 B2 | IO — User I/O |
| 引脚 B3 | IO — User I/O |
| 引脚 B4 | VCCINT — Core supply voltage (1.5V) |
| 引脚 C1 | IO — User I/O |
| 引脚 C2 | GND — Ground |
| 引脚 C3 | VCCIO — I/O supply voltage |
| 引脚 C4 | IO — User I/O |
| 引脚 D1 | VCCINT — Core supply voltage (1.5V) |
| 引脚 D2 | IO — User I/O |
| 引脚 D3 | IO — User I/O |
| 引脚 D4 | GND — Ground |
典型应用
EP1S20F672C6 适用于 6 应用s: Telecommunications Line Cards, Digital Signal Processing (DSP) Co-Processors, Software-Defined Radio (SDR) Base Stations, High-Speed Video Processing, ASIC Prototyping Platforms, Industrial Data Acquisition Systems.
Telecommunications Line Cards
The EP1S20F672C6 fits telecommunications line card designs because its 18,460 logic elements, TriMatrix memory, and high-speed transceiver channels support line-rate packet processing, framer implementations, and backplane SERDES. Its 426 user I/Os are sufficient for parallel bus connections to network processors and TDM framers. The dedicated DSP blocks handle echo cancellation and channel filtering operations at wire speed, while the 1.6 Mbit embedded memory provides packet buffering without external SRAM. Combined with commercial 0 to +85C temperature rating and the 672-BGA footprint's controlled-impedance signal routing, it serves well in central-office and base-station equipment.
推荐
Digital Signal Processing (DSP) Co-Processors
The EP1S20F672C6 is well suited for DSP co-processing because its dedicated hardware DSP blocks deliver 9-bit, 18-bit, and 36-bit multiply-accumulate operations ideal for FIR filters, FFT butterflies, and baseband processing. With approximately 80 DSP blocks running at 250 MHz, the device can sustain tens of billions of MAC operations per second. Its 18,460 logic elements handle control logic and interfacing, while 1,669,248 bits of TriMatrix memory provides coefficient storage and data buffering. Quartus II's DSP Builder tool chain accelerates algorithm implementation. Designers benefit from reduced BOM cost by replacing multiple DSP chips with one Stratix, while preserving flexibility for algorithm updates.
推荐
Software-Defined Radio (SDR) Base Stations
The EP1S20F672C6 supports SDR base station designs because its combination of high-speed ADC interface capability, embedded memory for sample buffering, and DSP blocks for channelization makes it suitable for multi-carrier signal processing. The 426 user I/Os connect to RF front-end ADCs/DACs and baseband interface logic, while dedicated transceiver channels carry digitized IF samples between boards. Its reprogrammability enables protocol updates (GSM, UMTS, LTE) without hardware changes. With 18,460 LEs handling FPGA fabric glue logic and the TriMatrix memory storing waveform coefficients, the device supports real-time baseband processing at commercial temperature in central-office environments.
推荐
High-Speed Video Processing
The EP1S20F672C6 fits high-speed video processing designs because its parallel logic fabric, embedded memory, and 426 I/Os handle multi-channel SDI, DVI, or Camera Link video streams with frame buffering and real-time pixel processing. With 1.6 Mbit TriMatrix memory, the device stores multiple video lines for pipelined filtering, scaling, and chroma conversion operations. The high I/O count supports 10-bit or 12-bit color depth at HD-SDI rates. Quartus II's Video and Image Processing Suite provides optimized IP cores for deinterlacing, scaling, and color space conversion, reducing development time for broadcast and medical imaging equipment.
推荐
ASIC Prototyping Platforms
The EP1S20F672C6 is widely used in ASIC prototyping because its high logic density (18,460 LEs) and 426 user I/Os accommodate partitioned ASIC RTL with sufficient capacity for sub-million-gate designs. Multiple EP1S20F672C6 devices can be paralleled on a prototyping board to validate ASIC functionality before tape-out. Embedded memory provides verification scratchpad space, while high-speed transceivers model ASIC-to-ASIC die-to-die interfaces. Quartus II's incremental compilation supports multi-FPGA partitioning flows. The commercial temperature rating suits lab validation environments, and the 672-BGA package offers the signal integrity required for 100+ MHz prototype operation.
推荐
Industrial Data Acquisition Systems
The EP1S20F672C6 fits industrial data acquisition because its high-speed ADC interface capability, DSP blocks for digital filtering, and 426 I/Os support multi-channel simultaneous sampling at rates up to 200 MSPS per channel. The 1.6 Mbit TriMatrix memory provides circular buffer storage for continuous sample streams, while DSP blocks implement real-time FIR and decimation filters. With commercial 0 to +85C temperature rating, it serves factory-floor and laboratory instrumentation. Industrial-grade EP1S20F672I6 variants extend the operating range for harsher environments, while the 672-BGA package's mechanical stability withstands industrial vibration and thermal cycling.
推荐
推荐产品汇总
工程参考数据： EP1S20F672C6 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EP1S20F672C7 | EP1S20F672C7N | EP1S20F672I6N | EP1S25F672C6 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | 672-ball FineLine BGA | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same |
| Logic Elements | 18,460 LEs | 18,460 LEs (same die) | 18,460 LEs (same die) | 18,460 LEs (same die) | 25,660 LEs (+39%) |
| Speed Grade | C6 (-6) | C7 (-7, faster Fmax) | C7 (-7, faster Fmax) | I6 (industrial temp, -6) | C6 (-6) |
| Embedded Memory | 1,669,248 bits | 1,669,248 bits (same) | 1,669,248 bits (same) | 1,669,248 bits (same) | 1,944,576 bits (+16%) |
| User I/Os | 426 | 426 (same) | 426 (same) | 426 (same) | 426 (same) |
| Temperature Range | 0 to +85C (Commercial) | 0 to +85C (Commercial) | 0 to +85C (Commercial) | -40C to +100C (Industrial) | 0 to +85C (Commercial) |
| Lead-Free (N suffix) | No (non-N) | No (non-N) | Yes (lead-free) | Yes (lead-free) | No (non-N) |
关键差异点
- Higher logic density than the EP1S10 family member （对比 EP1S10F672C6)
- Lower cost and broader availability than the faster speed-grade variant （对比 EP1S20F672C7)
- Same-footprint industrial temperature upgrade available （对比 EP1S20F672I6N)
设计说明
The EP1S20F672C6 requires multiple power rails: VCCINT core (1.5V nominal), VCCIO (programmable 1.5V/1.8V/2.5V/3.3V per bank), and VCC_PLL for PLL analog supply. Decouple each rail with 0.1 µF ceramic capacitors placed within 5 mm of each power pin, plus bulk capacitors of 100 µF or larger at the board voltage regulator outputs. Total power consumption scales with clock frequency and toggle rate; estimate 3-5W typical and 8-10W worst-case for a fully utilized EP1S20. Use the Quartus II PowerPlay analyzer to obtain accurate power estimates for your design before finalizing the power supply design.
The 672-ball FineLine BGA package has a 1.0 mm ball pitch, requiring precise PCB manufacturing with laser-drilled microvias or via-in-pad technology. Implement at least 6 PCB layers with dedicated ground and power planes to provide proper signal return paths for high-speed LVDS pairs and high-speed transceivers. Use differential pair routing with 100 Ω characteristic impedance for LVDS signals and 50 Ω single-ended for general-purpose I/O. The exposed die paddle underneath the BGA must be soldered to a thermal pad connected to ground for heat dissipation.
Place the EP1S20F672C6 close to associated memory devices (DDR SDRAM, QDR SRAM) to minimize trace lengths on high-speed memory interfaces. Match trace lengths within ±25 mils for DDR data strobes (DQS) and within ±50 mils for DDR address/command signals. For high-speed LVDS transmit pairs, use 100 Ω differential impedance with length matching to ±5 mils. The Quartus II pin planner should be used during schematic capture to assign I/O standards and locations before finalizing the PCB layout - changing I/O bank assignments late in design may require significant layout rework.
Common pitfalls when designing with EP1S20F672C6 include: (1) using modern Quartus Prime software which does NOT support first-generation Stratix - legacy Quartus II versions 4.0-13.0sp1 are required; (2) confusing the EP1S20 with the pin-incompatible EP1S25 (despite both using F672 package, ball maps differ and bitstreams are not interchangeable); (3) assuming JTAG chain works in-circuit - configure the JTAG chain order using the Quartus II programmer before relying on boundary-scan testing; (4) forgetting that this part is obsolete and may have multi-month lead times for production orders.
合规信息
RoHS compliance and lead-free status not explicitly stated in the verified web data. The 'N' suffix variants (e.g. EP1S20F672C6N) are lead-free per Altera's naming convention. AEC-Q100 not applicable - this is an FPGA, not an automotive-grade ASIC.