EP1S20F672I7 vs EP1S20B672C7N 对比
详细并排对比 EP1S20F672I7 出自 Intel 和 EP1S20B672C7N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1S20F672I7 | EP1S20B672C7N |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $199.50 | $320.00 |
| Family | Stratix (first generation) | Stratix (original) |
| Logic Elements (LEs) | 18,460 | 18,460 |
| Maximum RAM Bits | 1,669,248 | — |
| DSP Blocks | [DATA_NEEDED: exact DSP block count] | — |
| Maximum User I/Os | 426 | — |
| Supply Voltage (VCCINT core) | 1.5 V | — |
| Logic Family | CMOS | CMOS |
| 封装 | 672-BBGA (FineLine BGA), 35 x 35 mm, 1.27 mm pitch | — |
| 工作温度 | -40C to +85C (industrial grade, I7 suffix) | 0 °C to 85 °C (Commercial Extended) |
| Configuration Modes | Passive Serial, Passive Parallel, JTAG | — |
| Number of Pins / Balls | 672 | 672 |
| 安装类型 | Surface Mount (BGA) | Surface Mount (BGA) |
| Clock Management PLLs | [DATA_NEEDED: PLL count] | — |
| RoHS 状态 | unknown | [DATA_NEEDED: RoHS compliance] |
| Lead-Free / Finish | SnPb (e0 per Partstack datasheet extract) | — |
| MSL 等级 | unknown | 3 (per JEDEC J-STD-020) |
| Status | Last Time Buy (per distributor notices) | — |
| Series | — | Stratix |
| Process Technology | — | 0.13 µm CMOS |
| LABs / CLBs | — | 1,846 |
| Embedded Memory Bits | — | 1,669,248 bits |
| Maximum User I/O | — | 426 |
| Package Type | — | 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch) |
| Supply Voltage (Core, VCCINT) | — | 1.5 V |
| Speed Grade | — | -7 |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |