EP1S30B956C6 vs EP1S40B956C6 对比
详细并排对比 EP1S30B956C6 出自 Altera 和 EP1S40B956C6 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1S30B956C6 | EP1S40B956C6 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $78.00 | $1,078.40 |
| Family | Stratix | Stratix |
| Logic Elements (LEs) | 32,470 | — |
| Logic Array Blocks (LABs) | 3,247 | 4,125 |
| Embedded Memory Bits | 3,317,184 (approximately 3.4 Mbit) | — |
| Maximum User I/O | 683 | — |
| Process Technology | 130 nm CMOS | 0.13 um CMOS |
| Core Voltage (VCCINT) | 1.5 V | — |
| 工作温度 | 0 C to 85 C (Commercial) | 0C to 85C |
| Speed Grade | C6 | 6 (commercial, slowest) |
| 封装 | 956-ball FCBGA (BGA-956), 40 x 40 mm, 1.27 mm pitch | BGA-956 (956-BBGA, FCBGA) |
| 安装类型 | Surface Mount | Surface Mount |
| Maximum Internal Frequency | 450.05 MHz (per family datasheet) | — |
| DSP Blocks | Yes (Stratix DSP blocks) | Embedded multiplier blocks |
| PLLs | Up to 12 | Multiple phase-locked loops |
| Configuration Modes | Passive Serial (PS), Passive Parallel (PP), JTAG | — |
| RoHS 状态 | Not confirmed - pre-RoHS part | — |
| MSL 等级 | [DATA_NEEDED: MSL level] | — |
| Lead-Free | Unknown | — |
| Logic Elements / Cells | — | 41,250 |
| CLB Equivalents / Registers | — | 46,970 |
| User I/O Pins | — | 683 |
| Package Size | — | 40 x 40 mm |
| Ball Pitch | — | 1.27 mm |
| Core Supply Voltage | — | 1.5 V |
| Logic Family | — | CMOS |
| Embedded Memory | — | TriMatrix (M512, M4K, M-RAM blocks) |
| Lead-Free / RoHS | — | Per Altera/Intel datasheet |