EP1S30B956C6 vs EP1S40B956C6 Vergleich
Detaillierter Direktvergleich von EP1S30B956C6 von Altera und EP1S40B956C6 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1S30B956C6 | EP1S40B956C6 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $78,00 | $1.078,40 |
| Family | Stratix | Stratix |
| Logic Elements (LEs) | 32,470 | — |
| Logic Array Blocks (LABs) | 3,247 | 4,125 |
| Embedded Memory Bits | 3,317,184 (approximately 3.4 Mbit) | — |
| Maximum User I/O | 683 | — |
| Process Technology | 130 nm CMOS | 0.13 um CMOS |
| Core Voltage (VCCINT) | 1.5 V | — |
| Betriebstemperatur | 0 C to 85 C (Commercial) | 0C to 85C |
| Speed Grade | C6 | 6 (commercial, slowest) |
| Gehäuse | 956-ball FCBGA (BGA-956), 40 x 40 mm, 1.27 mm pitch | BGA-956 (956-BBGA, FCBGA) |
| Montageart | Surface Mount | Surface Mount |
| Maximum Internal Frequency | 450.05 MHz (per family datasheet) | — |
| DSP Blocks | Yes (Stratix DSP blocks) | Embedded multiplier blocks |
| PLLs | Up to 12 | Multiple phase-locked loops |
| Configuration Modes | Passive Serial (PS), Passive Parallel (PP), JTAG | — |
| RoHS-Status | Not confirmed - pre-RoHS part | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| Lead-Free | Unknown | — |
| Logic Elements / Cells | — | 41,250 |
| CLB Equivalents / Registers | — | 46,970 |
| User I/O Pins | — | 683 |
| Package Size | — | 40 x 40 mm |
| Ball Pitch | — | 1.27 mm |
| Core Supply Voltage | — | 1.5 V |
| Logic Family | — | CMOS |
| Embedded Memory | — | TriMatrix (M512, M4K, M-RAM blocks) |
| Lead-Free / RoHS | — | Per Altera/Intel datasheet |