EP1S40F1020C5N vs EP1S40F1020C5GA 对比

详细并排对比 EP1S40F1020C5N 出自 Intel 和 EP1S40F1020C5GA 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1S40F1020C5N EP1S40F1020C5GA
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $280.00 $171.00
Family Stratix —
Logic Elements (LE) 41,250 41,250
Logic Array Blocks (LAB) 4,125 —
Embedded Memory Bits 3,423,744 —
Maximum User I/Os 773 —
Process Technology 130 nm CMOS —
Core Voltage 1.5 V —
Maximum Internal Frequency 500 MHz —
Speed Grade C5 (commercial, slowest) C5
Temperature Grade Commercial Extended —
封装 1020-ball FBGA (FineLine BGA) 1020-BBGA (FineLine BGA)
安装类型 Surface Mount Surface Mount
PLLs Yes (multiple, enhanced PLL) —
DSP Blocks Yes (embedded multiplier blocks) Embedded multiplier blocks (count per Stratix datasheet family)
External Memory Support DDR SDRAM, QDR SRAM, FCRAM, ZBT —
Configuration Scheme Passive serial, active serial, JTAG —
RoHS 状态 Unknown - verify with manufacturer Unknown - non-GA suffix commercial part
Lead-Free Unknown Yes (per Altera/Intel policy at release)
Series — Stratix
Total RAM Bits — 3,423,744
User I/O Count — 773
工作温度 — 0C to +85C (Commercial)
Process Node — 0.13 µm CMOS with 9-layer metal
Supply Voltage (Core) — [DATA_NEEDED: VCCINT value]
I/O Bank Count — [DATA_NEEDED: bank count]
PLL Count — Up to 12 enhanced PLLs (per Stratix family)
High-Speed Transceivers — Up to 12 channels (per Stratix family, variant dependent)
Configuration Method — JTAG, Passive Serial, Altera EPC device
MSL 等级 — [DATA_NEEDED: MSL rating]

数据手册与资源

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