EP1S60F1020 vs EP1S60F1020C6N 对比

详细并排对比 EP1S60F1020 出自 Altera 和 EP1S60F1020C6N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EP1S60F1020 EP1S60F1020 - Stratix 57K LEs, 1020-BGA FPGA | Altera

EP1S60F1020 - Stratix 57K LEs, 1020-BGA FPGA | Altera

EP1S60F1020 ⚠ 最后一次采购

规格对比

参数 EP1S60F1020 EP1S60F1020C6N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $3,995.00 $195.00
Series Stratix Stratix
Family Altera Stratix (EP1S) Stratix (EP1S)
Process Technology 0.13 um CMOS —
Logic Elements (LEs) 57,120 57,120
Logic Array Blocks (LABs) 5,712 —
Total RAM Bits 5,215,104 —
Embedded Multipliers (DSP Blocks) [DATA_NEEDED: DSP block count] —
User I/Os 773 —
PLLs [DATA_NEEDED: PLL count, nominally 12 for Stratix EP1S60] —
封装 1020-BGA (FineLine FBGA) —
Core Voltage 1.5 V —
Operating Temperature (base part) Commercial (0C to +85C) —
Speed Grade (base part) [DATA_NEEDED: trailing suffix needed for explicit grade] —
安装类型 Surface Mount (BGA) Surface Mount (BGA)
MSL 等级 [DATA_NEEDED: MSL rating] [DATA_NEEDED: MSL rating]
RoHS 状态 [DATA_NEEDED: verify per part suffix] Compliant (per 'N' suffix)
I/O Standard Support LVDS, LVPECL, SSTL, HSTL, PCI/PCI-X —
Configuration Memory SRAM-based, requires external configuration device —
Logic Cells — 6,570 blocks (per chipdig datasheet summary)
Embedded RAM (Total Bits) — 5,215,104 bits
Embedded Multipliers — 773 (18x18)
Maximum User I/O Pins — Per datasheet, package-dependent (F1020 variant)
Package Type — 1020-ball FBGA (FineLine BGA), 33 x 33 mm, 1 mm pitch
Logic Family / Process — CMOS, 0.13 µm
工作温度 — 0°C to +85°C (Commercial)
电源电压 — Per datasheet (Stratix Device Handbook Vol. 1)
Speed Grade — C6 (mid-tier)
Lead-Free / Pb-Free — Yes (suffix 'N')
Configuration — JTAG / Passive Serial / Fast Passive Parallel via MSEL pins
PLL Count — 12 (per Stratix family datasheet)
Memory Block Types — TriMatrix (M512, M4K, M-RAM)

数据手册与资源

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