EP20K600CB652C7E5 vs EP20K600CB652C7ES 对比

详细并排对比 EP20K600CB652C7E5 出自 Intel 和 EP20K600CB652C7ES 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K600CB652C7E5 EP20K600CB652C7ES
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $175.00 $195.00
Family APEX 20KC APEX 20KC
Typical Gate Count 600K gates —
Logic Elements / Macros 24,320 —
Maximum User I/O 488 488
Embedded Memory (EAB bits) 311,296 bits —
封装 652-ball FineLine BGA —
Core Voltage 1.8 V —
Process Technology 0.15 um CMOS 0.15 µm CMOS
工作温度 0C to +85C (commercial, suffix C7) 0 °C to +85 °C (commercial)
Speed Grade 7 (-1 speed bin equivalent, E5 suffix) —
PLL Count 4 —
Supported I/O Standards LVTTL, LVCMOS, PCI, SSTL, HSTL —
Configuration Scheme Passive Serial / JTAG / EPC16 / EPC8 —
RoHS 状态 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
生命周期状态 Obsolete - last time buy has passed —
Logic Elements — 24,320
System Gates — 600,000
Maximum System Gates — 1,053,840
Embedded Memory Bits — 311,296
Embedded System Blocks (ESB) — 26
User I/O (this package) — 488 (652-BGA)
Supply Voltage - Core — 1.71 V to 1.89 V (1.8 V nominal)
Maximum Internal Clock Frequency — 1666.6 MHz
Propagation Delay — 1.6 ns
Package Type — 652-ball FineLine BGA
JEDEC Package Code — S-PBGA-B652
Configuration Modes — Passive Serial, Passive Parallel, JTAG
JTAG Boundary Scan — IEEE 1149.1 compliant
PLLs — 4
安装类型 — Surface Mount (BGA)

数据手册与资源

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