EP20K600CB652C7E5 vs EP20K600CB652C7ES Comparison

Detailed side-by-side comparison of EP20K600CB652C7E5 by Intel and EP20K600CB652C7ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K600CB652C7E5 EP20K600CB652C7ES
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $175.00 $195.00
Family APEX 20KC APEX 20KC
Typical Gate Count 600K gates β€”
Logic Elements / Macros 24,320 β€”
Maximum User I/O 488 488
Embedded Memory (EAB bits) 311,296 bits β€”
Package 652-ball FineLine BGA β€”
Core Voltage 1.8 V β€”
Process Technology 0.15 um CMOS 0.15 Β΅m CMOS
Operating Temperature 0C to +85C (commercial, suffix C7) 0 Β°C to +85 Β°C (commercial)
Speed Grade 7 (-1 speed bin equivalent, E5 suffix) β€”
PLL Count 4 β€”
Supported I/O Standards LVTTL, LVCMOS, PCI, SSTL, HSTL β€”
Configuration Scheme Passive Serial / JTAG / EPC16 / EPC8 β€”
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Lifecycle Status Obsolete - last time buy has passed β€”
Logic Elements β€” 24,320
System Gates β€” 600,000
Maximum System Gates β€” 1,053,840
Embedded Memory Bits β€” 311,296
Embedded System Blocks (ESB) β€” 26
User I/O (this package) β€” 488 (652-BGA)
Supply Voltage - Core β€” 1.71 V to 1.89 V (1.8 V nominal)
Maximum Internal Clock Frequency β€” 1666.6 MHz
Propagation Delay β€” 1.6 ns
Package Type β€” 652-ball FineLine BGA
JEDEC Package Code β€” S-PBGA-B652
Configuration Modes β€” Passive Serial, Passive Parallel, JTAG
JTAG Boundary Scan β€” IEEE 1149.1 compliant
PLLs β€” 4
Mounting Type β€” Surface Mount (BGA)

Datasheets & Resources

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