EP2A15B724C vs EP2A15B724C7 对比

详细并排对比 EP2A15B724C 出自 Altera 和 EP2A15B724C7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A15B724C EP2A15B724C7
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $195.00 $125.00
Family APEX II APEX II
Logic Elements (LEs) 16,640 —
Maximum User I/O Pins 492 —
Embedded RAM 425,984 bits —
封装 724-Ball FCBGA (FineLine BGA) 724-BBGA, FCBGA (35 mm x 35 mm)
Process Technology 0.18 micron CMOS 0.15 um all-layer copper
Maximum System Gates Up to 1.5M gates (family-level) —
Embedded System Blocks (ESBs) Configurable as dual-port RAM / ROM / FIFO —
Interconnect MultiTrack, deterministic —
I/O Standards LVTTL, LVCMOS, LVDS, PCI, GTL+ (family-level) —
PLLs Yes (family-level, up to 4 per device) —
工作温度 [DATA_NEEDED: operating temperature grade] 0 C to 85 C (TJ)
安装类型 Surface Mount (BGA) Surface Mount (BGA)
MSL 等级 [DATA_NEEDED: MSL rating] —
RoHS 状态 [DATA_NEEDED: RoHS compliance] unknown
Speed Grade C (per suffix; specific speed bin [DATA_NEEDED]) C7 (per part suffix)
JTAG / Configuration IEEE 1149.1 JTAG; passive serial / PS configuration supported (family-level) —
Manufacturer — Altera (acquired by Intel)
System Gates — 600,000
Logic Elements / Cells — 16,640
Total RAM Bits — 425,984
Number of I/O — 492
Core Voltage — 1.425 V to 1.575 V
Maximum Internal Frequency — 500 MHz
LVDS Support — True-LVDS up to 1 Gbps
Interface Standards — True-LVDS, LVPECL, PCML, HyperTransport
Configuration Modes — Passive Serial, Passive Parallel, JTAG

数据手册与资源

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