EP2A25F672C9N vs EP2A25F672ES 对比

详细并排对比 EP2A25F672C9N 出自 Intel 和 EP2A25F672ES 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A25F672C9N EP2A25F672ES
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $195.00 $198.00
Family APEX II APEX II
Logic Elements / Cells 24320 —
System Gates Approx. 900000 —
Maximum User I/O 492 —
Operating Frequency 236 MHz —
Core Supply Voltage (VCCINT) 1.425 V to 1.575 V (nominal 1.5 V) —
Process Technology 0.15 µm all-layer copper, up to 8 metal layers 0.15 µm CMOS
封装 672-ball FineLine BGA (F672), 27 × 27 mm, 1.00 mm pitch 672-ball FC-FBGA
安装类型 Surface Mount (BGA) —
Seated Height (max) 2.100 mm —
Propagation Delay 2.23 ns —
Logic Family CMOS —
工作温度 0 °C to +85 °C (commercial, C9 grade) —
I/O Standards Supported LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, LVDS, LVPECL, PCML, HyperTransport —
LVDS Data Rate Up to 1 Gbps (True-LVDS) —
Configuration Interface Serial / Parallel PROM, JTAG, passive parallel (enhanced) —
Embedded Memory Enhanced System Blocks (ESBs) for dual-port RAM —
Design Software Quartus II (v5.1 or later) —
RoHS 状态 Compliant (per distributor listings) Compliant
Logic Elements — 24,320
Maximum Gates — 900,000
Embedded System Blocks (ESBs) — 24
Maximum Embedded RAM — 1.4 Mbit
Maximum User I/O Pins — 492
Core Voltage — 1.5 V
Maximum System Clock Frequency — 500 MHz
Number of PLLs — 4
I/O Banks — 16
Supported I/O Standards — LVTTL, LVCMOS, PCI, LVDS, LVPECL, HSTL
Configuration Mode — Serial / Parallel / JTAG
工作温度范围 — [DATA_NEEDED: operating temperature range]

数据手册与资源

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