EP2A25F672I6 vs EP2A25F672C8 对比
详细并排对比 EP2A25F672I6 出自 Intel 和 EP2A25F672C8 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2A25F672I6 | EP2A25F672C8 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $178.00 | $951.18 |
| Family | APEX II | APEX II (EP2A25) |
| Logic Elements (typical gates) | 25,000 | — |
| Fabric Architecture | SRAM-based LUT | — |
| Process Technology | 0.18 µm CMOS | 0.15 microm CMOS, 8-layer copper interconnect |
| 封装 | 672-ball FineLine BGA (FBGA-672) | 672-FBGA (FineLine BGA, 27x27 mm, 1.0 mm pitch) |
| Core Voltage | 1.5 V | — |
| Configuration Method | External SRAM configuration device (EPC series) | — |
| Temperature Grade | Industrial (-40 °C to +100 °C ambient) | — |
| Speed Grade | 6 | C8 |
| Embedded Memory | Embedded System Blocks (ESB), dual-port RAM / CAM | ESB blocks (dual-port RAM, FIFO, CAM, ROM) |
| DSP Blocks | MultiCore dedicated multipliers | — |
| Boundary Scan | JTAG (IEEE 1149.1) compliant | — |
| Clock Management | Dedicated PLL / clock tree circuitry | — |
| I/O Bank Count | [DATA_NEEDED: number of user I/O banks] | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | Non-compliant (legacy product) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL 等级 | [DATA_NEEDED: moisture sensitivity level] | — |
| 安装类型 | Surface Mount (BGA) | Surface Mount |
| Logic Elements | — | 25,000 (typical gates) |
| Maximum System Gates | — | 40,960 |
| Macrocells / Embedded Logic | — | 2,432 macros |
| User I/O Count | — | 492 |
| Propagation Delay (tpd) | — | 1.69 ns |
| 工作温度 | — | 0 C to 85 C (commercial) |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI-X, GTL+, SSTL-2/3, HSTL, LVDS, LVPECL |
| LVDS Data Rate | — | 1 Gbps |
| PLL Count | — | 4 |
| I/O Banks | — | 16 |