EP2A40F672C6 vs EP2A40F672C6N 对比

详细并排对比 EP2A40F672C6 出自 Altera 和 EP2A40F672C6N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A40F672C6 EP2A40F672C6N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $105.00 $165.00
Family APEX II APEX II
Device EP2A40 —
Logic Elements (typical) 40,000 —
Maximum System Gates [DATA_NEEDED: maximum system gates] 1,125,000
Embedded System Blocks (ESBs) [DATA_NEEDED: ESB count] 160
Maximum User I/O Pins [DATA_NEEDED: max user I/O count] [DATA_NEEDED: maximum user I/O count]
封装 672-ball FineLine BGA (FBGA-672) 672-ball FineLine BGA
Speed Grade C6 (commercial) C6 (per part number suffix)
工作温度 Commercial (0C to +85C) Commercial (0C to +85C)
Process Technology 0.18-micron CMOS SRAM-based, 0.18 um (per family datasheet)
Configuration Memory SRAM-based —
JTAG Support Yes (IEEE 1149.1) —
PLL Support Yes —
安装类型 Surface Mount (BGA) Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Lead-Free [DATA_NEEDED: lead-free status] —
Lifecycle Obsolete / EOL (per Intel/Altera product discontinuation notice) —
Logic Elements — 40,000
Embedded RAM Bits — 442,368
Core Voltage — 1.5 V
I/O Standards Supported — LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V
Configuration Methods — Passive Serial, Passive Parallel, JTAG
PLL Count — [DATA_NEEDED: PLL count]

数据手册与资源

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