EP2A40F672C6 vs EP2A40F672C6N Comparación
Comparación detallada lado a lado de EP2A40F672C6 por Altera y EP2A40F672C6N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2A40F672C6 | EP2A40F672C6N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $105,00 | $165,00 |
| Family | APEX II | APEX II |
| Device | EP2A40 | — |
| Logic Elements (typical) | 40,000 | — |
| Maximum System Gates | [DATA_NEEDED: maximum system gates] | 1,125,000 |
| Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | 160 |
| Maximum User I/O Pins | [DATA_NEEDED: max user I/O count] | [DATA_NEEDED: maximum user I/O count] |
| Encapsulado | 672-ball FineLine BGA (FBGA-672) | 672-ball FineLine BGA |
| Speed Grade | C6 (commercial) | C6 (per part number suffix) |
| Temperatura de funcionamiento | Commercial (0C to +85C) | Commercial (0C to +85C) |
| Process Technology | 0.18-micron CMOS | SRAM-based, 0.18 um (per family datasheet) |
| Configuration Memory | SRAM-based | — |
| JTAG Support | Yes (IEEE 1149.1) | — |
| PLL Support | Yes | — |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Lifecycle | Obsolete / EOL (per Intel/Altera product discontinuation notice) | — |
| Logic Elements | — | 40,000 |
| Embedded RAM Bits | — | 442,368 |
| Core Voltage | — | 1.5 V |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V |
| Configuration Methods | — | Passive Serial, Passive Parallel, JTAG |
| PLL Count | — | [DATA_NEEDED: PLL count] |