EP2A40F672C6N vs EP2A40F672C6 对比

详细并排对比 EP2A40F672C6N 出自 Intel 和 EP2A40F672C6 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A40F672C6N EP2A40F672C6
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $165.00 $105.00
Family APEX II APEX II
Logic Elements 40,000 —
Maximum System Gates 1,125,000 [DATA_NEEDED: maximum system gates]
Embedded RAM Bits 442,368 —
Embedded System Blocks (ESBs) 160 [DATA_NEEDED: ESB count]
Maximum User I/O Pins [DATA_NEEDED: maximum user I/O count] [DATA_NEEDED: max user I/O count]
Core Voltage 1.5 V —
I/O Standards Supported LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V —
封装 672-ball FineLine BGA 672-ball FineLine BGA (FBGA-672)
工作温度 Commercial (0C to +85C) Commercial (0C to +85C)
Speed Grade C6 (per part number suffix) C6 (commercial)
Configuration Methods Passive Serial, Passive Parallel, JTAG —
安装类型 Surface Mount Surface Mount (BGA)
RoHS 状态 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Process Technology SRAM-based, 0.18 um (per family datasheet) 0.18-micron CMOS
PLL Count [DATA_NEEDED: PLL count] —
Device — EP2A40
Logic Elements (typical) — 40,000
Configuration Memory — SRAM-based
JTAG Support — Yes (IEEE 1149.1)
PLL Support — Yes
Lead-Free — [DATA_NEEDED: lead-free status]
Lifecycle — Obsolete / EOL (per Intel/Altera product discontinuation notice)

数据手册与资源

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