EP2A40F672C6N vs EP2A40F672C6 Comparación
Comparación detallada lado a lado de EP2A40F672C6N por Intel y EP2A40F672C6 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2A40F672C6N | EP2A40F672C6 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $165,00 | $105,00 |
| Family | APEX II | APEX II |
| Logic Elements | 40,000 | — |
| Maximum System Gates | 1,125,000 | [DATA_NEEDED: maximum system gates] |
| Embedded RAM Bits | 442,368 | — |
| Embedded System Blocks (ESBs) | 160 | [DATA_NEEDED: ESB count] |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count] | [DATA_NEEDED: max user I/O count] |
| Core Voltage | 1.5 V | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V | — |
| Encapsulado | 672-ball FineLine BGA | 672-ball FineLine BGA (FBGA-672) |
| Temperatura de funcionamiento | Commercial (0C to +85C) | Commercial (0C to +85C) |
| Speed Grade | C6 (per part number suffix) | C6 (commercial) |
| Configuration Methods | Passive Serial, Passive Parallel, JTAG | — |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Process Technology | SRAM-based, 0.18 um (per family datasheet) | 0.18-micron CMOS |
| PLL Count | [DATA_NEEDED: PLL count] | — |
| Device | — | EP2A40 |
| Logic Elements (typical) | — | 40,000 |
| Configuration Memory | — | SRAM-based |
| JTAG Support | — | Yes (IEEE 1149.1) |
| PLL Support | — | Yes |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Lifecycle | — | Obsolete / EOL (per Intel/Altera product discontinuation notice) |