EP2AGZ225FF35C4G vs EP2AGZ225FF35C3G 对比
详细并排对比 EP2AGZ225FF35C4G 出自 Intel 和 EP2AGZ225FF35C3G 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2AGZ225FF35C4G | EP2AGZ225FF35C3G |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $0.00 | $868.40 |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Manufacturer | Intel | — |
| Product Family | FPGA | — |
| User I/O | 554 I/O | — |
| 封装 | 1152FBGA | 1152-ball Flip-Chip BGA (FF35) |
| Package Type | Fine-pitch ball grid array | — |
| Logic Elements | [DATA_NEEDED: logic element count] | — |
| Embedded Memory | [DATA_NEEDED: embedded memory capacity] | [DATA_NEEDED: Mbits] |
| DSP Blocks | [DATA_NEEDED: DSP block count] | [DATA_NEEDED: count] |
| Transceivers | [DATA_NEEDED: transceiver count] | Up to 16 channels |
| 工作温度 | [DATA_NEEDED: operating temperature range] | 0C to +85C (Commercial) |
| 电源电压 | [DATA_NEEDED: supply voltage] | — |
| I/O Standards | [DATA_NEEDED: supported I/O standards] | — |
| Configuration Method | [DATA_NEEDED: configuration method] | — |
| RoHS 状态 | unknown | Compliant |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | not_applicable | — |
| Lead-Free Status | unknown | — |
| Halogen-Free Status | unknown | — |
| Family | — | Arria II GZ |
| Series | — | Arria II |
| Logic Elements (LE) | — | 225,000 |
| Package Size | — | 35 mm x 35 mm |
| Speed Grade | — | C3 |
| Transceiver Data Rate (max) | — | 6.375 Gbps |
| User I/O Banks | — | [DATA_NEEDED: count] |
| Maximum User I/O | — | [DATA_NEEDED: pin count] |
| Process Technology | — | 40 nm TSMC |
| Memory Controller Support | — | DDR3, DDR2, QDR II+ |
| PCI Express Hard IP | — | Yes (Gen1/Gen2) |
| 安装类型 | — | Surface Mount (BGA) |
| MSL 等级 | — | 3 (per JEDEC J-STD-020) |
| Lead-Free | — | Yes |