EP2S180F1020C5 vs EP2S180F1020C3 对比

详细并排对比 EP2S180F1020C5 出自 Intel 和 EP2S180F1020C3 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2S180F1020C5 EP2S180F1020C3
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $3,357.86 $1,280.00
Series Stratix II Stratix II
Family Stratix II —
Logic Elements (LE) 179,400 —
Configurable Logic Blocks (CLBs) 71,760 —
Logic Array Blocks (LABs) 8,970 8,970
Total RAM Bits 9,383,040 —
User I/O Pins 742 —
封装 1020-BBGA, FCBGA (33 x 33 mm, 1.0 mm pitch) 1020-ball FBGA (flip-chip BGA)
Core Voltage 1.15 V to 1.25 V 1.2 V
Process Technology 90 nm CMOS —
工作温度 0 C to +85 C (commercial) Commercial (0C to +85C)
Speed Grade C5 C3
安装类型 Surface Mount (BGA) Surface Mount
RoHS 状态 [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS status]
Configuration Mode JTAG / Passive Serial / Passive Parallel / Active Serial —
Number of Transceivers [DATA_NEEDED: transceiver_count] —
Device Family — EP2S180
Equivalent Logic Elements (LEs) — 179,400
Embedded Memory (RAM bits) — 9,383,040
Maximum User I/Os — 742
Process Node — 90 nm, all-layer copper SRAM
DSP Blocks — Dedicated high-speed multipliers
Memory Interfaces Supported — DDR2 SDRAM, QDRII SRAM, RLDRAM II
I/O Standards — LVDS, LVPECL, SSTL, HSTL
Configuration Method — SRAM-based (volatile, requires boot device)
Development Toolchain — Quartus II / Quartus Prime

数据手册与资源

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