EP2SGX130GF40C3N vs EP2SGX130GF40C4NES 对比

详细并排对比 EP2SGX130GF40C3N 出自 Intel 和 EP2SGX130GF40C4NES 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2SGX130GF40C3N EP2SGX130GF40C4NES
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $1,485.00 $1,380.00
Family Stratix II GX Stratix II GX
Logic Elements 132,540 132,540
Embedded Memory 6.7 Mbits Approximately 4.5 Mbits (TriMatrix)
Embedded Multipliers (18x18) 252 —
User I/O Count 734 —
Transceiver Count 40 channels —
Max Transceiver Data Rate 6.375 Gbps —
Process Technology 90 nm 90 nm CMOS
Core Voltage 1.2 V 1.2 V
封装 1508-ball FC-FBGA —
安装类型 Surface Mount (flip-chip BGA) Surface Mount (flip-chip BGA)
工作温度 0C to +85C (commercial) Commercial Extended (per N suffix)
Speed Grade C3 C4 (speed grade -4)
Configuration Mode Passive Serial / Fast Passive Parallel / JTAG —
RoHS 状态 Compliant —
Logic Blocks / ALMs — Approximately 53,000 ALMs
Maximum Transceiver Data Rate — 6.375 Gbps
Transceiver Channels — Up to 20 (4 to 20, device-dependent)
User I/O Pins — 734
Total Package Pins — 1508 (FC-FBGA ball grid)
Package Code — GF40 (FC-FBGA, 40x40 mm, 1.0 mm pitch)
Internal Operating Frequency — Up to 717 MHz
PLL Blocks — 8
DSP Blocks — Yes (variable, see datasheet)
Lead-Free / RoHS — Yes (LEAD FREE per datasheet family code)
MSL 等级 — Per JEDEC J-STD-020, typically MSL-4 or higher [DATA_NEEDED: exact MSL level]
JEDEC Standard Reference — MS-034AAU-1

数据手册与资源

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