EP2SGX130GF40C3N vs EP2SGX130GF40C4NES Comparison

Detailed side-by-side comparison of EP2SGX130GF40C3N by Intel and EP2SGX130GF40C4NES by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP2SGX130GF40C3N EP2SGX130GF40C4NES
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $1,485.00 $1,380.00
Family Stratix II GX Stratix II GX
Logic Elements 132,540 132,540
Embedded Memory 6.7 Mbits Approximately 4.5 Mbits (TriMatrix)
Embedded Multipliers (18x18) 252 β€”
User I/O Count 734 β€”
Transceiver Count 40 channels β€”
Max Transceiver Data Rate 6.375 Gbps β€”
Process Technology 90 nm 90 nm CMOS
Core Voltage 1.2 V 1.2 V
Package 1508-ball FC-FBGA β€”
Mounting Type Surface Mount (flip-chip BGA) Surface Mount (flip-chip BGA)
Operating Temperature 0C to +85C (commercial) Commercial Extended (per N suffix)
Speed Grade C3 C4 (speed grade -4)
Configuration Mode Passive Serial / Fast Passive Parallel / JTAG β€”
RoHS Status Compliant β€”
Logic Blocks / ALMs β€” Approximately 53,000 ALMs
Maximum Transceiver Data Rate β€” 6.375 Gbps
Transceiver Channels β€” Up to 20 (4 to 20, device-dependent)
User I/O Pins β€” 734
Total Package Pins β€” 1508 (FC-FBGA ball grid)
Package Code β€” GF40 (FC-FBGA, 40x40 mm, 1.0 mm pitch)
Internal Operating Frequency β€” Up to 717 MHz
PLL Blocks β€” 8
DSP Blocks β€” Yes (variable, see datasheet)
Lead-Free / RoHS β€” Yes (LEAD FREE per datasheet family code)
MSL Level β€” Per JEDEC J-STD-020, typically MSL-4 or higher [DATA_NEEDED: exact MSL level]
JEDEC Standard Reference β€” MS-034AAU-1

Datasheets & Resources

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