EP2SGX130GF40C3NES vs EP2SGX130GF40C4NES 对比

详细并排对比 EP2SGX130GF40C3NES 出自 Altera 和 EP2SGX130GF40C4NES 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2SGX130GF40C3NES EP2SGX130GF40C4NES
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $124.00 $1,380.00
Family Stratix II GX Stratix II GX
Logic Elements 132540 132,540
Logic Array Blocks (LABs) 7047 —
Maximum Internal Frequency 778.82 MHz —
Process Technology 90 nm CMOS 90 nm CMOS
Core Voltage 1.2 V 1.2 V
Transceiver Channels 4 to 20 (per device family configuration) Up to 20 (4 to 20, device-dependent)
Maximum Transceiver Data Rate 6.375 Gbps 6.375 Gbps
Transceiver Feature Embedded SERDES with Clock/Data Recovery (CRU) —
存储器类型 TriMatrix embedded memory (distributed RAM, block RAM, shift register) —
封装 1508-ball FC-FBGA (40 x 40 mm, 1 mm pitch) —
Operating Temperature Grade Commercial Extended —
Terminal Form Ball (BGA) —
安装类型 Surface Mount Surface Mount (flip-chip BGA)
RoHS 状态 Lead-free compliant (per package code MS-034AAU-1) —
Series EP2SGX130 —
Logic Blocks / ALMs — Approximately 53,000 ALMs
User I/O Pins — 734
Total Package Pins — 1508 (FC-FBGA ball grid)
Package Code — GF40 (FC-FBGA, 40x40 mm, 1.0 mm pitch)
Speed Grade — C4 (speed grade -4)
Internal Operating Frequency — Up to 717 MHz
Embedded Memory — Approximately 4.5 Mbits (TriMatrix)
PLL Blocks — 8
DSP Blocks — Yes (variable, see datasheet)
Lead-Free / RoHS — Yes (LEAD FREE per datasheet family code)
MSL 等级 — Per JEDEC J-STD-020, typically MSL-4 or higher [DATA_NEEDED: exact MSL level]
工作温度 — Commercial Extended (per N suffix)
JEDEC Standard Reference — MS-034AAU-1

数据手册与资源

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