EP3SE260H780C3N vs EP3SE260H780C4N 对比
详细并排对比 EP3SE260H780C3N 出自 Intel 和 EP3SE260H780C4N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP3SE260H780C3N | EP3SE260H780C4N |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $1,325.00 | $1,395.00 |
| Series | Stratix® III E | — |
| Logic Elements (LE) | 255,000 | — |
| Embedded Memory (bits) | 16,672,768 | — |
| Number of LABs/CLBs | 10,200 | — |
| User I/Os | 488 | — |
| Number of Pins / Balls | 780 | — |
| 封装 | 780-BBGA, FCBGA (H780) | 780-ball FCBGA (Flip Chip BGA) |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度 | 0 °C to +85 °C (C grade, commercial) | 0C to +85C (commercial) |
| Process Technology | 40 nm CMOS | — |
| Maximum Core Frequency | [DATA_NEEDED: maximum core frequency MHz] | — |
| Supply Voltage (VCCINT) | [DATA_NEEDED: VCCINT nominal V] | — |
| Transceivers | [DATA_NEEDED: number of embedded transceivers and max data rate] | — |
| DSP Blocks | [DATA_NEEDED: number of DSP blocks and precision] | — |
| RoHS 状态 | Compliant (lead-free 'N' suffix) | — |
| 湿敏等级（MSL） | [DATA_NEEDED: MSL level per JEDEC J-STD-020] | 3 (168 hours) |
| Configuration Method | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel | Serial/Parallel via Quartus II |
| Design Toolchain | Altera Quartus II (legacy); Intel Quartus Prime | — |
| Family | — | Stratix III E (Enhanced) |
| Logic Elements | — | 255,000 |
| Logic Array Blocks (LABs) | — | 10,200 |
| Total RAM Bits | — | 16,672,768 |
| Embedded Memory | — | M9K and M144K blocks |
| User I/O Pins | — | 488 |
| DSP Blocks (18x18 Multipliers) | — | 768 |
| PLLs | — | 12 |
| Process Node | — | 65 nm CMOS |
| Core Voltage | — | 0.86 V to 1.15 V |
| Maximum Core Clock Frequency | — | 450 MHz |