EP3SL200H780C3 vs EP3SL200H780C3N 对比

详细并排对比 EP3SL200H780C3 出自 Altera 和 EP3SL200H780C3N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP3SL200H780C3 EP3SL200H780C3N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $5,900.00 $4,995.00
Manufacturer Intel (formerly Altera) —
Series Stratix III L —
Device EP3SL200 —
封装 780-ball FCBGA (H780) 780-Ball FCBGA (HBGA), 29 x 29 mm
Logic Elements 200,000 200,000
Logic Array Blocks (LABs) 8,000 8,000
User I/O Pins 488 —
Embedded Memory Bits 10,901,520 10,901,504 bits
Speed Grade 3 (slowest of Stratix III bins) C3 (commercial, -3 speed)
工作温度 Commercial grade (0C to +85C, exact range [DATA_NEEDED]) 0C to +85C (commercial)
安装类型 Surface Mount (BGA) Surface Mount
MSL 等级 3 (168 Hours) 3
Sub-Family Stratix III L (lower-power logic variant) —
Transceivers [DATA_NEEDED: count and speed] 24 channels, up to 3.75 Gbps
DSP Blocks [DATA_NEEDED: count] 384
RoHS 状态 [DATA_NEEDED: confirmed in datasheet] —
Lead-Free / Halogen-Free [DATA_NEEDED] —
Family — Stratix III L (low-power)
Process Node — 40 nm
User I/Os — 488
Maximum Internal Clock Frequency — 800 MHz
Voltage - Core — 0.9 V / 1.0 V (core, VCC)
Voltage - I/O — 1.2 V to 3.3 V (VCCIO banks)
Lead-Free / RoHS — Yes
Mounting Pitch — 1.0 mm ball pitch
PLLs — 12 (Stratix III PLL array)
Configuration — JTAG IEEE Std 1149.1, passive/active serial

数据手册与资源

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