EP3SL50F484I4L vs EP3SL50F484I4LG 对比

详细并排对比 EP3SL50F484I4L 出自 Intel 和 EP3SL50F484I4LG 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP3SL50F484I4L EP3SL50F484I4LG
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $658.26 $945.00
Series Stratix III L (Low Power) EP3SL50
Family Stratix III Stratix III L
Logic Elements (LE) 47,500 —
Embedded Memory Bits 2,184,192 bits (~273 KB) —
User I/O Pins 296 —
封装 484-ball FBGA (FCBGA) 484-Ball FCBGA (FBGA)
Speed Grade 4 I4 (fast)
工作温度 0 °C to 85 °C (commercial, per DigiKey listing) -40C to +100C (Industrial)
电源电压 0.9 V core (family-typical) 0.85 V / 1.1 V / 1.2 V / 2.5 V / 3.3 V (multi-rail)
Process Technology 65 nm low-power CMOS —
安装类型 Surface Mount Surface Mount
Lead-Free / RoHS Yes (RoHS compliant) —
Configuration Modes Passive Serial, Fast Passive Parallel, JTAG —
Transceivers Family supports up to 4 transceivers per family datasheet [DATA_NEEDED: transceiver channel count]
DSP Blocks Family supports up to 384 18x18 multipliers (family-level) [DATA_NEEDED: DSP block count]
Logic Elements — 47,500
Embedded Memory — 2,184,192 bits (273 KB)
User I/Os — 296
Process Node — 40 nm
RoHS 状态 — Compliant
Lead-Free — Yes
Total I/O Banks — [DATA_NEEDED: I/O bank count]
Configuration Memory — SRAM-based
Configuration Interface — JTAG / Passive Serial / Fast Passive Parallel

数据手册与资源

浏览全部产品 创建 BOM 获取报价