EP610IDC-10 vs EP610DC-10 对比
详细并排对比 EP610IDC-10 出自 Intel 和 EP610DC-10 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP610IDC-10 | EP610DC-10 |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $8.85 | $7.95 |
| Device Family | Altera Classic EPLD | Altera Classic EPLD |
| Logic Capacity | 300 usable gates | — |
| Macrocell Count | 16 macrocells | — |
| Pin-to-Pin Logic Delay (tpd) | 10 ns | — |
| Maximum Counter Frequency (fCNT) | 100 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | — |
| I/O Logic Compatibility | 100% TTL emulation | — |
| Technology | CMOS, UV-erasable (windowed ceramic) | CMOS, EPROM-based (UV-erasable) |
| Package Type | 24-pin Ceramic DIP (CDIP) | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 20 | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| 工作温度范围 | 0 °C to +70 °C (commercial) | — |
| Programmable Interconnect | Yes (on-chip) | — |
| In-System Programmability | Yes (via MAX+PLUS II) | — |
| Boundary-Scan Test | Yes (per device documentation) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status of CDIP-10 variant] | [DATA_NEEDED: not stated in verified web data] |
| 安装类型 | Through-hole | Through-Hole |
| Macrocells | — | 16 |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | — | 10 ns |
| Speed Grade | — | -10 |
| 封装 | — | 24-pin CDIP (Ceramic DIP, windowed) |
| 电源电压 | — | 5 V (single supply) |
| 工作温度 | — | 0C to +70C (commercial) |
| Logic Elements | — | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | — | UV-erasable EPROM |
| Reprogrammable | — | Yes (UV erase window on package) |