EP610IDC-10 vs EP610DC-10 Comparison
Detailed side-by-side comparison of EP610IDC-10 by Intel and EP610DC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610IDC-10 | EP610DC-10 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.85 | $7.95 |
| Device Family | Altera Classic EPLD | Altera Classic EPLD |
| Logic Capacity | 300 usable gates | β |
| Macrocell Count | 16 macrocells | β |
| Pin-to-Pin Logic Delay (tpd) | 10 ns | β |
| Maximum Counter Frequency (fCNT) | 100 MHz | β |
| Supply Voltage (VCC) | 5 V (nominal) | β |
| I/O Logic Compatibility | 100% TTL emulation | β |
| Technology | CMOS, UV-erasable (windowed ceramic) | CMOS, EPROM-based (UV-erasable) |
| Package Type | 24-pin Ceramic DIP (CDIP) | β |
| Dedicated Inputs | 4 | β |
| I/O Pins | 20 | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| Operating Temperature Range | 0 Β°C to +70 Β°C (commercial) | β |
| Programmable Interconnect | Yes (on-chip) | β |
| In-System Programmability | Yes (via MAX+PLUS II) | β |
| Boundary-Scan Test | Yes (per device documentation) | β |
| RoHS Status | [DATA_NEEDED: RoHS status of CDIP-10 variant] | [DATA_NEEDED: not stated in verified web data] |
| Mounting Type | Through-hole | Through-Hole |
| Macrocells | β | 16 |
| Maximum Pipelined Data Rate | β | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | β | 10 ns |
| Speed Grade | β | -10 |
| Package | β | 24-pin CDIP (Ceramic DIP, windowed) |
| Supply Voltage | β | 5 V (single supply) |
| Operating Temperature | β | 0C to +70C (commercial) |
| Logic Elements | β | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | β | UV-erasable EPROM |
| Reprogrammable | β | Yes (UV erase window on package) |