EP610IDC-10 vs EP610IDC-15 对比
详细并排对比 EP610IDC-10 出自 Intel 和 EP610IDC-15 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP610IDC-10 | EP610IDC-15 |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $8.85 | $9.95 |
| Device Family | Altera Classic EPLD | Altera Classic EPLD |
| Logic Capacity | 300 usable gates | — |
| Macrocell Count | 16 macrocells | — |
| Pin-to-Pin Logic Delay (tpd) | 10 ns | — |
| Maximum Counter Frequency (fCNT) | 100 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | 4.75 V to 5.25 V (5 V nominal) |
| I/O Logic Compatibility | 100% TTL emulation | — |
| Technology | CMOS, UV-erasable (windowed ceramic) | — |
| Package Type | 24-pin Ceramic DIP (CDIP) | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 20 | 24 (per package; macrocell-programmable) |
| 工作温度范围 | 0 °C to +70 °C (commercial) | — |
| Programmable Interconnect | Yes (on-chip) | — |
| In-System Programmability | Yes (via MAX+PLUS II) | — |
| Boundary-Scan Test | Yes (per device documentation) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status of CDIP-10 variant] | [DATA_NEEDED: RoHS status of CerDIP variant] |
| 安装类型 | Through-hole | Through-hole |
| Macrocells | — | 16 |
| Usable Gates | — | 300 |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Frequency | — | 66 MHz |
| 工作温度 | — | 0C to +70C (commercial) |
| Process Technology | — | CMOS, UV-erasable / OTP |
| 封装 | — | 24-pin CerDIP (ceramic DIP) |
| Logic-Block Architecture | — | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | — | UV-erasable, OTP-compatible |
| Development Tool | — | MAX+PLUS II |
| Programming Current | — | 11.0 mA typical (per Classic family datasheet) |