EP610IDC-10 vs EP610IDC-15 비교
다음의 상세 나란히 비교: EP610IDC-10 제조: Intel 및 EP610IDC-15 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP610IDC-10 | EP610IDC-15 |
|---|---|---|
| 브랜드 | Intel | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | 최종 구매 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $8.85 | $9.95 |
| Device Family | Altera Classic EPLD | Altera Classic EPLD |
| Logic Capacity | 300 usable gates | — |
| Macrocell Count | 16 macrocells | — |
| Pin-to-Pin Logic Delay (tpd) | 10 ns | — |
| Maximum Counter Frequency (fCNT) | 100 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | 4.75 V to 5.25 V (5 V nominal) |
| I/O Logic Compatibility | 100% TTL emulation | — |
| Technology | CMOS, UV-erasable (windowed ceramic) | — |
| Package Type | 24-pin Ceramic DIP (CDIP) | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 20 | 24 (per package; macrocell-programmable) |
| 동작 온도 범위 | 0 °C to +70 °C (commercial) | — |
| Programmable Interconnect | Yes (on-chip) | — |
| In-System Programmability | Yes (via MAX+PLUS II) | — |
| Boundary-Scan Test | Yes (per device documentation) | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status of CDIP-10 variant] | [DATA_NEEDED: RoHS status of CerDIP variant] |
| 실장 유형 | Through-hole | Through-hole |
| Macrocells | — | 16 |
| Usable Gates | — | 300 |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Frequency | — | 66 MHz |
| 동작 온도 | — | 0C to +70C (commercial) |
| Process Technology | — | CMOS, UV-erasable / OTP |
| 패키지 | — | 24-pin CerDIP (ceramic DIP) |
| Logic-Block Architecture | — | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | — | UV-erasable, OTP-compatible |
| Development Tool | — | MAX+PLUS II |
| Programming Current | — | 11.0 mA typical (per Classic family datasheet) |