EP610SC-20 vs EP610SC-15 对比

详细并排对比 EP610SC-20 出自 Rochester Electronics 和 EP610SC-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Rochester Electronics
EP610SC-20 EP610SC-20 - 16-Macrocell Classic EPLD, 22ns, 5V, SOIC-24

EP610SC-20 - 16-Macrocell Classic EPLD, 22ns, 5V, SOIC-24

EP610SC-20 ✓ 量产中

规格对比

参数 EP610SC-20 EP610SC-15
品牌 Rochester Electronics Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 Obsolete
库存状态 有库存 有库存
单价(USD) $17.50 $11.00
Product Type EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EP610 —
Macrocells 16 —
Gate Equivalent 300 gates —
Propagation Delay (tPD) 22 ns 15 ns
Pipelined Data Rate up to 100 MHz —
Supply Voltage (VCC) 5 V 4.75 V to 5.25 V (5 V typical)
Technology CMOS with EPROM configuration —
封装 24-pin SOIC (PDSO24) —
安装类型 Surface Mount —
工作温度 Commercial (0C to +70C) [DATA_NEEDED: industrial/military grade availability] 0 °C to +70 °C (commercial)
Logic Levels 5V CMOS —
I/O Count [DATA_NEEDED: usable I/O count per datasheet pinout] —
Configuration Memory EPROM (UV-erasable in windowed variants, OTP in plastic) —
RoHS 状态 [DATA_NEEDED: confirm via Rochester product page] —
Manufacturer Rochester Electronics (authorized source for original Altera design) —
Product Family — Altera Classic EPLD
Number of Macrocells — 16
Usable Gates — 300
Maximum Operating Frequency (fMAX) — 83.3 MHz (typical)
Number of I/O Pins — 24 (package-limited)
Package Type — 24-pin SOP (SOIC-24, 300-mil)
Programmable Type — EPLD (EPROM-based, OTP for SC package)
Process Technology — CMOS
Architecture — Sum-of-products AND/OR with macrocell flip-flop
Programming Method — EPROM programmer (standard EPROM algorithm)
Lead-Free / RoHS — non-compliant (legacy Altera Classic family)
Erasability — One-time programmable for plastic SC package; ceramic windowed variants (LC/DM) are UV-erasable
Manufacturer Status — Discontinued; Rochester Electronics is the authorized lifecycle source

数据手册与资源

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