EP610SC-20 vs EP610SC-15 비교

다음의 상세 나란히 비교: EP610SC-20 제조: Rochester Electronics 및 EP610SC-15 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

Rochester Electronics
EP610SC-20 EP610SC-20 - 16-Macrocell Classic EPLD, 22ns, 5V, SOIC-24

EP610SC-20 - 16-Macrocell Classic EPLD, 22ns, 5V, SOIC-24

EP610SC-20 ✓ 활성

사양 비교

파라미터 EP610SC-20 EP610SC-15
브랜드 Rochester Electronics Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 활성 Obsolete
재고 상태 In Stock In Stock
단가 (USD) $17.50 $11.00
Product Type EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EP610 —
Macrocells 16 —
Gate Equivalent 300 gates —
Propagation Delay (tPD) 22 ns 15 ns
Pipelined Data Rate up to 100 MHz —
Supply Voltage (VCC) 5 V 4.75 V to 5.25 V (5 V typical)
Technology CMOS with EPROM configuration —
패키지 24-pin SOIC (PDSO24) —
실장 유형 Surface Mount —
동작 온도 Commercial (0C to +70C) [DATA_NEEDED: industrial/military grade availability] 0 °C to +70 °C (commercial)
Logic Levels 5V CMOS —
I/O Count [DATA_NEEDED: usable I/O count per datasheet pinout] —
Configuration Memory EPROM (UV-erasable in windowed variants, OTP in plastic) —
RoHS 상태 [DATA_NEEDED: confirm via Rochester product page] —
Manufacturer Rochester Electronics (authorized source for original Altera design) —
Product Family — Altera Classic EPLD
Number of Macrocells — 16
Usable Gates — 300
Maximum Operating Frequency (fMAX) — 83.3 MHz (typical)
Number of I/O Pins — 24 (package-limited)
Package Type — 24-pin SOP (SOIC-24, 300-mil)
Programmable Type — EPLD (EPROM-based, OTP for SC package)
Process Technology — CMOS
Architecture — Sum-of-products AND/OR with macrocell flip-flop
Programming Method — EPROM programmer (standard EPROM algorithm)
Lead-Free / RoHS — non-compliant (legacy Altera Classic family)
Erasability — One-time programmable for plastic SC package; ceramic windowed variants (LC/DM) are UV-erasable
Manufacturer Status — Discontinued; Rochester Electronics is the authorized lifecycle source

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