EP910DC-15 vs EP910ILC-15N 对比
详细并排对比 EP910DC-15 出自 Altera 和 EP910ILC-15N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N Obsolete规格对比
| 参数 | EP910DC-15 | EP910ILC-15N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.75 | $9.85 |
| Family | Altera Classic EPLD | Classic |
| Device Density | 900 usable gates | — |
| Macrocells | 24 | — |
| Logic Elements | [DATA_NEEDED: exact LE count] | — |
| Dedicated Inputs | 12 | — |
| Bidirectional I/O Pins | 12 | — |
| Flip-Flops | 10 | — |
| Product Terms per Macrocells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | 15 ns |
| Speed Grade | 15 | — |
| Supply Voltage (VCC) | 5 V (typical) | 4.75 V to 5.25 V (5 V nominal) |
| 工作温度 | 0C to +70C (commercial) | 0 C to +70 C (commercial) |
| Technology | CMOS EPROM, UV-erasable | — |
| 封装 | 24-pin ceramic DIP (DC) | PLCC-44 (J-lead, surface mount) |
| 安装类型 | Through-Hole | Surface Mount |
| MSL 等级 | [DATA_NEEDED: MSL level] | — |
| RoHS 状态 | [DATA_NEEDED: not explicitly stated in verified data] | Compliant |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Gates | — | 450 |
| Macro Cells | — | 24 |
| Maximum Operating Frequency | — | 66.6 MHz |
| User I/O Pins | — | 36 |
| Dedicated Input Pins | — | 16 |
| Process Technology | — | CMOS EPROM (one-time programmable) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Programming | — | EPROM / JTAG (Classic EP-series) |