EP910DC-40 vs EP910LC-30 对比

详细并排对比 EP910DC-40 出自 Altera 和 EP910LC-30 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP910DC-40 EP910LC-30
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $13.95 $22.50
Device Family Classic EPLD (EP910 series) —
Architecture PAL-type AND/OR, UV-erasable CMOS —
Macrocells 24 —
Dedicated Inputs 12 —
Bidirectional I/O Pins 24 —
Total Inputs to Logic Array 36 —
Product Terms 240 maximum —
Maximum Propagation Delay (tPD) 40 ns —
Maximum Operating Frequency (fMAX) 25 MHz —
Global Clocks 2 —
电源电压 5 V (typical for Classic EPLD family) —
Operating Temperature (Commercial) 0 °C to 70 °C —
封装 DIP-40 (ceramic, through-hole) —
安装类型 Through-Hole —
RoHS 状态 [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS status]
Programming Method UV-erase + EPROM programmer; on-board logic test circuitry —
Device Type — EPLD (Erasable Programmable Logic Device)
Macrocell Count — 24
Propagation Delay (tPD) — 30 ns (max)
Maximum Toggle Frequency — 62 MHz
Supply Voltage (VCC) — 5 V (nominal, TTL)
Process Technology — CMOS (EPROM-based)
Package Type — PDIP-40 (Plastic DIP, through-hole)
Operating Temperature Grade — Commercial (0C to +70C)
I/O Pin Count — 24
Dedicated Input Pins — 36 (including I/O)
Product Terms per Macrocell — Up to 16
Programming Technology — UV-erasable EPROM cell
Development Tool — Altera MAX+PLUS II
MSL 等级 — [DATA_NEEDED: MSL level]

数据手册与资源

浏览全部产品 创建 BOM 获取报价